In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Difference between revisions of "Hardware/Memory controller"

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{{Infobox MMIO
 
{{Infobox MMIO
 +
| ppc = None
 
| arm = Full
 
| arm = Full
 
| base = 0x0d8b4000
 
| base = 0x0d8b4000
Line 7: Line 8:
 
| latteirq = ???
 
| latteirq = ???
 
}}
 
}}
 +
 +
The Latte hardware implements AMBA (possibly rev 2.0) compliant AHB buses for communication to/from the Starbuck's CPU and assorted on-chip hardware blocks (DMA, for example).<br>
 +
One of such blocks appears to be a customized memory controller that is responsible for several tasks such as DDR configuration, flushing memory to/from the AHB and employing a custom memory protection solution dubbed MEM_BLOCK.<br>
 +
This controller appears to be an extension of the one that was previously used on the Wii.
 +
 
== Register List ==
 
== Register List ==
 
{{reglist|Memory Controller}}
 
{{reglist|Memory Controller}}
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{{rld|0x0d8b4406|16|MEM_BLOCK_ERROR_ADDR_LOW|MEM block protection violation's address (low)}}
 
{{rld|0x0d8b4406|16|MEM_BLOCK_ERROR_ADDR_LOW|MEM block protection violation's address (low)}}
 
{{rld|0x0d8b4408|16|MEM_BLOCK_ERROR_ADDR_HIGH|MEM block protection violation's address (high)}}
 
{{rld|0x0d8b4408|16|MEM_BLOCK_ERROR_ADDR_HIGH|MEM block protection violation's address (high)}}
−
{{rld|0x0d8b440e|16|MEM_UNK|Unknown}}
+
{{rld|0x0d8b440e|16|MEM_BLOCK_UNK|Unknown}}
−
{{rld|0x0d8b442a|16|MEM_UNK|Unknown}}
+
{{rld|0x0d8b442a|16|MEM_BLOCK_UNK|Unknown}}
−
{{rld|0x0d8b442c|16|MEM_UNK|Unknown}}
+
{{rld|0x0d8b442c|16|MEM_BLOCK_UNK|Unknown}}
−
{{rld|0x0d8b44c4|16|MEM_UNK|Unknown}}
+
{{rld|0x0d8b44c4|16|MEM_BLOCK_UNK|Unknown}}
 
{{rld|0x0d8b4472|16|MEM_BLOCK_ERROR_CID|MEM block protection violation's client ID}}
 
{{rld|0x0d8b4472|16|MEM_BLOCK_ERROR_CID|MEM block protection violation's client ID}}
 
{{rld|0x0d8b4474|16|MEM_BLOCK_ERROR|MEM block protection violation's state}}
 
{{rld|0x0d8b4474|16|MEM_BLOCK_ERROR|MEM block protection violation's state}}
−
{{rld|0x0d8b4494|16|MEM_UNK|Unknown}}
+
{{rld|0x0d8b4494|16|MEM_BLOCK_UNK|Unknown}}
−
{{rld|0x0d8b4492|16|MEM_UNK|Unknown}}
+
{{rld|0x0d8b4492|16|MEM_BLOCK_UNK|Unknown}}
 
|}
 
|}
 +
 
== Register Details ==
 
== Register Details ==

Revision as of 17:11, 14 April 2016

Memory controller
Access
EspressoNone
StarbuckFull
Registers
Base0x0d8b4000
Length???
Access size16 bits
Byte orderBig Endian
IRQs
Espresso???
Latte???
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The Latte hardware implements AMBA (possibly rev 2.0) compliant AHB buses for communication to/from the Starbuck's CPU and assorted on-chip hardware blocks (DMA, for example).
One of such blocks appears to be a customized memory controller that is responsible for several tasks such as DDR configuration, flushing memory to/from the AHB and employing a custom memory protection solution dubbed MEM_BLOCK.
This controller appears to be an extension of the one that was previously used on the Wii.

Register List

Memory Controller
Address Bits Name Description
0x0d8b4026 16 MEM_UNK Unknown
0x0d8b4200 16 MEM_UNK Unknown
0x0d8b4210 16 MEM_UNK Unknown
0x0d8b4212 16 MEM_UNK Unknown
0x0d8b4214 16 MEM_UNK Unknown
0x0d8b4216 16 MEM_UNK Unknown
0x0d8b4218 16 MEM_UNK Unknown
0x0d8b421a 16 MEM_UNK Unknown
0x0d8b421c 16 MEM_UNK Unknown
0x0d8b4226 16 MEM_REFRESH_FLAG Unknown
0x0d8b4228 16 MEM_FLUSH_MASK Mask of the AHB connected client to flush memory to/from
0x0d8b422a 16 MEM_FLUSH_ACK AHB memory flushing acknowledged state
0x0d8b4268 16 MEM_UNK Unknown
0x0d8b426a 16 MEM_UNK Unknown
0x0d8b426c 16 MEM_UNK Unknown
0x0d8b426e 16 MEM_UNK Unknown
0x0d8b4270 16 MEM_UNK Unknown
0x0d8b4272 16 MEM_UNK Unknown
0x0d8b4274 16 MEM_UNK Unknown
0x0d8b4276 16 MEM_UNK Unknown
0x0d8b4278 16 MEM_UNK Unknown
0x0d8b427a 16 MEM_UNK Unknown
0x0d8b427c 16 MEM_UNK Unknown
0x0d8b427e 16 MEM_UNK Unknown
0x0d8b4280 16 MEM_UNK Unknown
0x0d8b4282 16 MEM_UNK Unknown
0x0d8b42a6 16 MEM_UNK Unknown
0x0d8b42b4 16 MEM_UNK Unknown
0x0d8b42b6 16 MEM_UNK Unknown
0x0d8b42ba 16 MEM_UNK Unknown
0x0d8b42c0 16 MEM_UNK Unknown
0x0d8b42c2 16 MEM_UNK Unknown
0x0d8b42c4 16 MEM_SEQ_REG_VAL DDR sequential register's value to read/write
0x0d8b42c6 16 MEM_SEQ_REG_ADDR DDR sequential register's address to read/write
0x0d8b42cc 16 MEM_EDRAM_REFRESH_CTRL EDRAM refresh settings
0x0d8b42ce 16 MEM_EDRAM_REFRESH_VAL EDRAM refresh value
0x0d8b42d4 16 MEM_MEM1_COMPAT_MODE Unknown
0x0d8b42d8 16 MEM_UNK Unknown
0x0d8b4300 16 MEM_SEQ0_REG_VAL DDR sequential register's value to read/write
0x0d8b4302 16 MEM_SEQ0_REG_ADDR DDR sequential register's address to read/write
0x0d8b4400 16 MEM_BLOCK_MEM0_CFG MEM block protection configuration for MEM0
0x0d8b4402 16 MEM_BLOCK_MEM1_CFG MEM block protection configuration for MEM1
0x0d8b4404 16 MEM_BLOCK_MEM2_CFG MEM block protection configuration for MEM2
0x0d8b4406 16 MEM_BLOCK_ERROR_ADDR_LOW MEM block protection violation's address (low)
0x0d8b4408 16 MEM_BLOCK_ERROR_ADDR_HIGH MEM block protection violation's address (high)
0x0d8b440e 16 MEM_BLOCK_UNK Unknown
0x0d8b442a 16 MEM_BLOCK_UNK Unknown
0x0d8b442c 16 MEM_BLOCK_UNK Unknown
0x0d8b44c4 16 MEM_BLOCK_UNK Unknown
0x0d8b4472 16 MEM_BLOCK_ERROR_CID MEM block protection violation's client ID
0x0d8b4474 16 MEM_BLOCK_ERROR MEM block protection violation's state
0x0d8b4494 16 MEM_BLOCK_UNK Unknown
0x0d8b4492 16 MEM_BLOCK_UNK Unknown

Register Details

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