Hardware/Memory controller

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Memory controller
Access size16 bits
Byte orderBig Endian
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The Latte hardware implements AMBA (possibly rev 2.0) compliant AHB buses for communication to/from the Starbuck's CPU and assorted on-chip hardware blocks (DMA, for example).
One of such blocks appears to be a customized memory controller that is responsible for several tasks such as DDR configuration, flushing memory to/from the AHB and employing a custom memory protection solution dubbed MEM_BLOCK.
This controller appears to be an extension of the one that was previously used on the Wii.

Register List

Memory Controller
Address Bits Name Description
0x0d8b4000 16 MEM_MARR0_START Memory Protection
0x0d8b4002 16 MEM_MARR0_END
0x0d8b4004 16 MEM_MARR1_START
0x0d8b4006 16 MEM_MARR1_END
0x0d8b4008 16 MEM_MARR2_START
0x0d8b400a 16 MEM_MARR2_END
0x0d8b400c 16 MEM_MARR3_START
0x0d8b400e 16 MEM_MARR3_END
0x0d8b4010 16 MEM_MARR_CONTROL MARR{0-3} permissions
0x0d8b4012 16 MEM_CP_BW_DIAL Bandwidth Dial (Command Processor)
0x0d8b4014 16 MEM_TC_BW_DIAL Bandwidth Dial (Texture Control)
0x0d8b4016 16 MEM_PE_BW_DIAL Bandwidth Dial (Pixel Engine)
0x0d8b4018 16 MEM_CPUR_BW_DIAL Bandwidth Dial (CPU read)
0x0d8b401a 16 MEM_CPUW_BW_DIAL Bandwidth Dial (CPU write)
0x0d8b401c 16 MEM_INT_ENBL MARR interrupt enable
0x0d8b401e 16 MEM_INT_STAT MARR interrupt status
0x0d8b4020 16 MEM_INT_CLR MARR interrupt clear/mask (?)
0x0d8b4022 16 MEM_INT_ADDRL MARR interrupt address (lo bits)
0x0d8b4024 16 MEM_INT_ADDRH MARR interrupt address (hi bits)
0x0d8b4026 16 MEM_REFRESH Memory refresh
0x0d8b4028 16 MEM_CONFIG Memory configuration
0x0d8b402a 16 MEM_LATENCY Memory latency
0x0d8b402c 16 MEM_RDTORD Memory read to read
0x0d8b402e 16 MEM_RDTOWR Memory read to write
0x0d8b4030 16 MEM_WRTORD Memory write to read
0x0d8b4032 16 MEM_CP_REQCOUNTH Memory Request Count (Command Processor) (hi bits)
0x0d8b4034 16 MEM_CP_REQCOUNTL Memory Request Count (Command Processor) (lo bits)
0x0d8b4036 16 MEM_TC_REQCOUNTH Memory Request Count (Texture Control) (hi bits)
0x0d8b4038 16 MEM_TC_REQCOUNTL Memory Request Count (Texture Control) (lo bits)
0x0d8b403a 16 MEM_CPUR_REQCOUNTH Memory Request Count (CPU read) (hi bits)
0x0d8b403c 16 MEM_CPUR_REQCOUNTL Memory Request Count (CPU read) (lo bits)
0x0d8b403e 16 MEM_CPUW_REQCOUNTH Memory Request Count (CPU write) (hi bits)
0x0d8b4040 16 MEM_CPUW_REQCOUNTL Memory Request Count (CPU write) (lo bits)
0x0d8b4042 16 MEM_DSP_REQCOUNTH Memory Request Count (DSP) (hi bits)
0x0d8b4044 16 MEM_DSP_REQCOUNTL Memory Request Count (DSP) (lo bits)
0x0d8b4046 16 MEM_IO_REQCOUNTH Memory Request Count (I/O) (hi bits)
0x0d8b4048 16 MEM_IO_REQCOUNTL Memory Request Count (I/O) (lo bits)
0x0d8b404a 16 MEM_VI_REQCOUNTH Memory Request Count (Video Interface) (hi bits)
0x0d8b404c 16 MEM_VI_REQCOUNTL Memory Request Count (Video Interface) (lo bits)
0x0d8b404e 16 MEM_PE_REQCOUNTH Memory Request Count (Pixel Engine) (hi bits)
0x0d8b4050 16 MEM_PE_REQCOUNTL Memory Request Count (Pixel Engine) (lo bits)
0x0d8b4052 16 MEM_RF_REQCOUNTH Memory Request Count (RF) (hi bits)
0x0d8b4054 16 MEM_RF_REQCOUNTL Memory Request Count (RF) (lo bits)
0x0d8b4056 16 MEM_FI_REQCOUNTH Memory Request Count (FI) (hi bits)
0x0d8b4058 16 MEM_FI_REQCOUNTL Memory Request Count (FI) (lo bits)
0x0d8b405a 16 MEM_DRV_STRENGTH Unknown
0x0d8b405c 16 MEM_REFRSH_THHD Unknown
0x0d8b4060 16 MEM_CPUAHMR_REQCOUNTH Memory Request Count (CPU AHM read) (hi bits)
0x0d8b4062 16 MEM_CPUAHMR_REQCOUNTL Memory Request Count (CPU AHM read) (lo bits)
0x0d8b4064 16 MEM_CPUAHMW_REQCOUNTH Memory Request Count (CPU AHM write) (hi bits)
0x0d8b4066 16 MEM_CPUAHMW_REQCOUNTL Memory Request Count (CPU AHM write) (lo bits)
0x0d8b4068 16 MEM_DMAAHMR_REQCOUNTH Memory Request Count (DMA AHM read) (hi bits)
0x0d8b406a 16 MEM_DMAAHMR_REQCOUNTL Memory Request Count (DMA AHM read) (lo bits)
0x0d8b406c 16 MEM_DMAAHMW_REQCOUNTH Memory Request Count (DMA AHM write) (hi bits)
0x0d8b406e 16 MEM_DMAAHMW_REQCOUNTL Memory Request Count (DMA AHM write) (lo bits)
0x0d8b4070 16 MEM_ACC_REQCOUNTH Memory Request Count (ACC) (hi bits)
0x0d8b4072 16 MEM_ACC_REQCOUNTL Memory Request Count (ACC) (lo bits)
0x0d8b4074 16 MEM_DDRREG_ADDR DDR register offset
0x0d8b4076 16 MEM_DDRREG_DATA DDR register data
0x0d8b4078 16 MEM_DRV_PSTRENGTH Unknown
0x0d8b4200 16 MEM_COMPAT Unknown
0x0d8b4202 16 MEM_PROT_REG Unknown
0x0d8b4204 16 MEM_PROT_SPL SPL protection enable/disable
0x0d8b4206 16 MEM_PROT_SPL_BASE SPL protection base address
0x0d8b4208 16 MEM_PROT_SPL_END SPL protection end address
0x0d8b420a 16 MEM_PROT_DDR DDR protection enable/disable
0x0d8b420c 16 MEM_PROT_DDR_BASE DDR protection base address
0x0d8b420e 16 MEM_PROT_DDR_END DDR protection end address
0x0d8b4210 16 MEM_COLSEL Unknown
0x0d8b4212 16 MEM_ROWSEL Unknown
0x0d8b4214 16 MEM_BANKSEL Unknown
0x0d8b4216 16 MEM_RANKSEL Unknown
0x0d8b4218 16 MEM_COLMSK Unknown
0x0d8b421a 16 MEM_ROWMSK Unknown
0x0d8b421c 16 MEM_BANKMSK Unknown
0x0d8b421e 16 MEM_PROT_SPL_ERR SPL protection error
0x0d8b4220 16 MEM_PROT_DDR_ERR DDR protection error
0x0d8b4222 16 MEM_PROT_SPL_MSK SPL protection mask
0x0d8b4224 16 MEM_PROT_DDR_MSK DDR protection mask
0x0d8b4226 16 MEM_RFSH Unknown
0x0d8b4228 16 MEM_AHMFLUSH AHB flush request
0x0d8b422a 16 MEM_AHMFLUSH_ACK AHB flush request acknowledgment
0x0d8b4268 16 MEM_SEQRD_HWM Unknown
0x0d8b426a 16 MEM_SEQWR_HWM Unknown
0x0d8b426c 16 MEM_SEQCMD_HWM Unknown
0x0d8b426e 16 MEM_CPUAHM_WR_T Unknown
0x0d8b4270 16 MEM_DMAAHM_WR_T Unknown
0x0d8b4272 16 MEM_DMAAHM0_WR_T Unknown
0x0d8b4274 16 MEM_DMAAHM1_WR_T Unknown
0x0d8b4276 16 MEM_PI_WR_T Unknown
0x0d8b4278 16 MEM_PE_WR_T Unknown
0x0d8b427a 16 MEM_IO_WR_T Unknown
0x0d8b427c 16 MEM_DSP_WR_T Unknown
0x0d8b427e 16 MEM_ACC_WR_T Unknown
0x0d8b4280 16 MEM_ARB_MAXWR Unknown
0x0d8b4282 16 MEM_ARB_MINRD Unknown
0x0d8b4284 16 MEM_PROF_CPUAHM Unknown
0x0d8b4286 16 MEM_PROF_CPUAHM0 Unknown
0x0d8b4288 16 MEM_PROF_DMAAHM Unknown
0x0d8b428a 16 MEM_PROF_DMAAHM0 Unknown
0x0d8b428c 16 MEM_PROF_DMAAHM1 Unknown
0x0d8b428e 16 MEM_PROF_PI Unknown
0x0d8b4290 16 MEM_PROF_VI Unknown
0x0d8b4292 16 MEM_PROF_IO Unknown
0x0d8b4294 16 MEM_PROF_DSP Unknown
0x0d8b4296 16 MEM_PROF_TC Unknown
0x0d8b4298 16 MEM_PROF_CP Unknown
0x0d8b429a 16 MEM_PROF_ACC Unknown
0x0d8b429c 16 MEM_RDPR_CPUAHM Unknown
0x0d8b429e 16 MEM_RDPR_CPUAHM0 Unknown
0x0d8b42a0 16 MEM_RDPR_DMAAHM Unknown
0x0d8b42a2 16 MEM_RDPR_DMAAHM0 Unknown
0x0d8b42a4 16 MEM_RDPR_DMAAHM1 Unknown
0x0d8b42a6 16 MEM_RDPR_PI Unknown
0x0d8b42a8 16 MEM_RDPR_VI Unknown
0x0d8b42aa 16 MEM_RDPR_IO Unknown
0x0d8b42ac 16 MEM_RDPR_DSP Unknown
0x0d8b42ae 16 MEM_RDPR_TC Unknown
0x0d8b42b0 16 MEM_RDPR_CP Unknown
0x0d8b42b2 16 MEM_RDPR_ACC Unknown
0x0d8b42b4 16 MEM_ARB_MAXRD Unknown
0x0d8b42b6 16 MEM_ARB_MISC Unknown
0x0d8b42b8 16 MEM_ARAM_EMUL Unknown
0x0d8b42ba 16 MEM_WRMUX Unknown
0x0d8b42bc 16 MEM_PERF Unknown
0x0d8b42be 16 MEM_PERF_READ Unknown
0x0d8b42c0 16 MEM_ARB_EXADDR Unknown
0x0d8b42c2 16 MEM_ARB_EXCMD Unknown
0x0d8b42c4 16 MEM_SEQ_DATA DDR SEQ register's value to read/write
0x0d8b42c6 16 MEM_SEQ_ADDR DDR SEQ register's address to read/write
0x0d8b42c8 16 MEM_BIST_DATA DDR BIST register's address to read/write
0x0d8b42ca 16 MEM_BIST_ADDR DDR BIST register's address to read/write
0x0d8b42cc 16 MEM_EDRAM_REFRESH_CTRL EDRAM refresh settings
0x0d8b42ce 16 MEM_EDRAM_REFRESH_VAL EDRAM refresh value
0x0d8b42d4 16 MEM_MEM1_COMPAT_MODE Unknown
0x0d8b42d6 16 MEM_CAFE_DDR_RANGE_TOP Unknown
0x0d8b42d8 16 MEM_UNK Unknown
0x0d8b4300 16 MEM_SEQ0_DATA DDR SEQ0 sequential register's value to read/write
0x0d8b4302 16 MEM_SEQ0_ADDR DDR SEQ0 sequential register's address to read/write
0x0d8b4400 16 MEM_BLOCK_MEM0_CFG MEM block protection configuration for MEM0
0x0d8b4402 16 MEM_BLOCK_MEM1_CFG MEM block protection configuration for MEM1
0x0d8b4404 16 MEM_BLOCK_MEM2_CFG MEM block protection configuration for MEM2
0x0d8b4406 16 MEM_BLOCK_ERROR_ADDR_LOW MEM block protection violation's address (low)
0x0d8b4408 16 MEM_BLOCK_ERROR_ADDR_HIGH MEM block protection violation's address (high)
0x0d8b440e 16 MEM_BLOCK_UNK Unknown
0x0d8b442a 16 MEM_BLOCK_UNK Unknown
0x0d8b442c 16 MEM_BLOCK_UNK Unknown
0x0d8b44c4 16 MEM_BLOCK_UNK Unknown
0x0d8b4472 16 MEM_BLOCK_ERROR_CID MEM block protection violation's client ID
0x0d8b4474 16 MEM_BLOCK_ERROR MEM block protection violation's state
0x0d8b4494 16 MEM_BLOCK_UNK Unknown
0x0d8b4492 16 MEM_BLOCK_UNK Unknown
0x0d8b464a 16 MEM_GPU_ENDIANNESS GPU endianness control

Register Details

MEM_MEM1_COMPAT_MODE (0x0d8b42d4)
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R/W
Field MODE

This register modifies the translation of addresses to MEM1 locations in blocks of 0x100 bytes. It is modified by cafe2wii while entering vWii mode.

The 25 bits of a MEM1 address can be split into 8 least significant bits of offset, left unmodified by the translation process, and 17 bits representing the block number.

In mode 0, no translation is applied. This mode is normally used in WiiU mode and during boot.

In mode 1, the 4 least significant bits of the block number are rotated left by 3 bits.

In mode 2, the 11 least significant bits of the block number are rotated left by 3 bits.

In mode 3, all 17 bits of the block number are rotated left by 3 bits. This mode is normally used in vWii mode.

Field Description
MODE MEM1 block translation mode