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== Buses ==
== Buses ==
−Each pair of I²C lines available as {{hw|Latte GPIOs}} appears to have an equivalent Latte controller. Since I²C
+Each pair of I²C lines available as {{hw|Latte GPIOs}} appears to have an equivalent Latte controller.
=== Bus 1 (AV encoder) ===
=== Bus 1 (AV encoder) ===
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== Registers ==
== Registers ==
−{{reglist|I²C Bus 1 Registers (AV encoder)}}
+{{reglist|I²C Bus 1 Master Registers (AV encoder)}}
−{{rld|0x0d800068|32|LT_AVE_I2C_INT_MASK|}}
+{{rld|0x0d800068|32|HW_I2CIOPINTEN|}}
−{{rld|0x0d80006c|32|LT_AVE_I2C_INT_STATE}}
+{{rld|0x0d80006c|32|HW_I2CIOPINTSTS}}
−{{rld|0x0d800250|32|LT_AVE_I2C_CLOCK|}}
+{{rld|0x0d800250|32|HW_I2CMCTRL|}}
−{{rld|0x0d800254|32|LT_AVE_I2C_INOUT_DATA}}
+{{rld|0x0d800254|32|HW_I2CMDATAWR}}
−{{rld|0x0d800258|32|LT_AVE_I2C_INOUT_CTRL}}
+{{rld|0x0d800258|32|HW_I2CMWREN}}
−{{rld|0x0d80025c|32|LT_AVE_I2C_INOUT_SIZE}}
+{{rld|0x0d80025c|32|HW_I2CMDATARD}}
|}
|}
Despite being in the Wood address space, these registers do not appear to be present on the original Wii.{{check}}
Despite being in the Wood address space, these registers do not appear to be present on the original Wii.{{check}}
−{{reglist|I²C Bus 3 Registers (SMC)}}
+{{reglist|I²C Bus 3 Master Registers (SMC)}}
−{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK}}
+{{rld|0x0d800570|32|LT_I2CMCTRL}}
−{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
+{{rld|0x0d800574|32|LT_I2CMDATAWR}}
−{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
+{{rld|0x0d800578|32|LT_I2CMWREN}}
−{{rld|0x0d80057c|32|LT_SMC_I2C_INOUT_SIZE}}
+{{rld|0x0d80057c|32|LT_I2CMDATARD}}
−{{rld|0x0d800580|32|LT_SMC_I2C_INT_MASK}}
+{{rld|0x0d800580|32|LT_I2CIOPINTEN}}
−{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
+{{rld|0x0d800584|32|LT_I2CIOPINTSTS}}
|}
|}