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== Registers ==
== Registers ==
{{reglist|I²C Bus 1 Master Registers (AV encoder)}}
{{reglist|I²C Bus 1 Master Registers (AV encoder)}}
−{{rld|0x0d800068|32|HW_I2CIOPINTEN|}}
+{{rld|0x0d800068|32|HW_I2CIOPINTEN|I2C interrupt enable}}
−{{rld|0x0d80006c|32|HW_I2CIOPINTSTS}}
+{{rld|0x0d80006c|32|HW_I2CIOPINTSTS|I2C interrupt status}}
−{{rld|0x0d800250|32|HW_I2CMCTRL|}}
+{{rld|0x0d800250|32|HW_I2CMCTRL|I2C master control}}
−{{rld|0x0d800254|32|HW_I2CMDATAWR}}
+{{rld|0x0d800254|32|HW_I2CMDATAWR|I2C master data write}}
−{{rld|0x0d800258|32|HW_I2CMWREN}}
+{{rld|0x0d800258|32|HW_I2CMWREN|I2C master write enable}}
−{{rld|0x0d80025c|32|HW_I2CMDATARD}}
+{{rld|0x0d80025c|32|HW_I2CMDATARD|I2C master data read}}
|}
|}
Line 40:
Line 40:
{{reglist|I²C Bus 3 Master Registers (SMC)}}
{{reglist|I²C Bus 3 Master Registers (SMC)}}
−{{rld|0x0d800570|32|LT_I2CMCTRL}}
+{{rld|0x0d800570|32|LT_I2CMCTRL|I2C master control}}
−{{rld|0x0d800574|32|LT_I2CMDATAWR}}
+{{rld|0x0d800574|32|LT_I2CMDATAWR|I2C master data write}}
−{{rld|0x0d800578|32|LT_I2CMWREN}}
+{{rld|0x0d800578|32|LT_I2CMWREN|I2C master write enable}}
−{{rld|0x0d80057c|32|LT_I2CMDATARD}}
+{{rld|0x0d80057c|32|LT_I2CMDATARD|I2C master data read}}
−{{rld|0x0d800580|32|LT_I2CIOPINTEN}}
+{{rld|0x0d800580|32|LT_I2CIOPINTEN|I2C interrupt enable}}
−{{rld|0x0d800584|32|LT_I2CIOPINTSTS}}
+{{rld|0x0d800584|32|LT_I2CIOPINTSTS|I2C interrupt status}}
|}
|}