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Hardware/Latte IRQs (view source)

Revision as of 00:56, 27 November 2023

1,783 bytes added ,  00:56, 27 November 2023
→‎IRQ Sources
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==IRQ Sources==
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The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
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{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
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IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LATTE).
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|- style="background-color: #ddd;"
+
 
−
! IRQ
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== IRQ Sources ==
 +
{| class="wikitable"
 +
|-
 +
! Bit
 +
! Group
 
! Description
 
! Description
 
|-
 
|-
−
| 0 || {{hw|Starbuck Timer}}
+
| 0 || ALL || TMR (Timer)
 +
|-
 +
| 0 || LATTE || SD2 ({{hw|SD Host Controller}} for eMMC)
 +
|-
 +
| 1 || ALL || FLA ({{hw|NAND Interface}})
 +
|-
 +
| 1 || LATTE || SD3 ({{hw|SD Host Controller}} for Toucan)
 +
|-
 +
| 2 || ALL || AES0 ({{hw|AES Engine}})
 +
|-
 +
| 2 || LATTE || EHCI1 ({{hw|USB Host Controller}})
 +
|-
 +
| 3 || ALL || SHA0 ({{hw|SHA-1 Engine}})
 +
|-
 +
| 3 || LATTE || OHCI10 ({{hw|USB Host Controller}})
 +
|-
 +
| 4 || ALL || EHCI0 ({{hw|USB Host Controller}})
 +
|-
 +
| 4 || LATTE || EHCI2 ({{hw|USB Host Controller}})
 +
|-
 +
| 5 || ALL || OHCI0 ({{hw|USB Host Controller}})
 +
|-
 +
| 5 || LATTE || OHCI20 ({{hw|USB Host Controller}})
 +
|-
 +
| 6 || ALL || OHCI1 ({{hw|USB Host Controller}})
 +
|-
 +
| 6 || LATTE || SATA ({{hw|SATA Controller}})
 +
|-
 +
| 7 || ALL || SD0 ({{hw|SD Host Controller}})
 +
|-
 +
| 7 || LATTE || Unknown
 +
|-
 +
| 8 || ALL || SD1 ({{hw|802.11 Wireless}})
 +
|-
 +
| 8 || LATTE || AES1 ({{hw|AES Engine}} for AESS)
 +
|-
 +
| 9 || ALL || Reserved
 +
|-
 +
| 9 || LATTE || SHA1 ({{hw|SHA-1 Engine}} for SHAS-1)
 +
|-
 +
| 10 || ALL || GPIPPC ({{hw|Latte GPIOs}} for Espresso)
 +
|-
 +
| 10 || LATTE || Unknown
 +
|-
 +
| 11 || ALL || GPIIOP ({{hw|Latte GPIOs}} for Starbuck)
 +
|-
 +
| 11 || LATTE || GPU7_GC
 +
|-
 +
| 12 || ALL || DBGINT
 +
|-
 +
| 12 || LATTE || IOP2X
 +
|-
 +
| 13 || ALL || VIPIWR
 +
|-
 +
| 13 || LATTE || PRIMARY_I2C (for Espresso)
 +
|-
 +
| 14 || ALL || SIEMU
 +
|-
 +
| 14 || LATTE || SECONDARY_I2C (for Starbuck)
 +
|-
 +
| 15 || ALL || SYSRSTB
 +
|-
 +
| 15 || LATTE || Reserved
 
|-
 
|-
−
| 1 || {{hw|NAND Interface}}
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| 16 || ALL || VIVSYNC
 
|-
 
|-
−
| 2 || {{hw|AES Engine}}
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| 16 || LATTE || Reserved
 
|-
 
|-
−
| 3 || {{hw|SHA-1 Engine}}
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| 17 || ALL || Power button
 
|-
 
|-
−
| 4 || {{hw|USB Host Controller}} (EHCI)
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| 17 || LATTE || Reserved
 
|-
 
|-
−
| 5 || {{hw|USB Host Controller}} (OHCI0)
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| 18 || ALL || DI
 
|-
 
|-
−
| 6 || {{hw|USB Host Controller}} (OHCI1)
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| 18 || LATTE || Reserved
 
|-
 
|-
−
| 7 || {{hw|SD Host Controller}}
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| 19 || ALL || Reserved
 
|-
 
|-
−
| 8 || {{hw|802.11 Wireless}}
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| 19 || LATTE || Reserved
 
|-
 
|-
−
| 9 || Unknown
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| 20 || ALL || EXI
 
|-
 
|-
−
| 10 || {{hw|Latte GPIOs}} (Espresso)
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| 20 || LATTE || Reserved
 
|-
 
|-
−
| 11 || {{hw|Latte GPIOs}} (Starbuck)
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| 21 || ALL || Reserved
 
|-
 
|-
−
| 12 || Unknown
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| 21 || LATTE || Reserved
 
|-
 
|-
−
| 13 || Undefined
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| 22 || ALL || Reserved
 
|-
 
|-
−
| 14 || Undefined
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| 22 || LATTE || Reserved
 
|-
 
|-
−
| 15 || Undefined
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| 23 || ALL || Reserved
 
|-
 
|-
−
| 16 || Undefined
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| 23 || LATTE || Reserved
 
|-
 
|-
−
| 17 || Power button (reset)
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| 24 || ALL || Reserved
 
|-
 
|-
−
| 18 || {{hw|Drive Interface}} (DI)
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| 24 || LATTE || Reserved
 
|-
 
|-
−
| 19 || Undefined
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| 25 || ALL || Reserved
 
|-
 
|-
−
| 20 || Unknown
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| 25 || LATTE || Reserved
 
|-
 
|-
−
| 21 || Undefined
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| 26 || ALL || Reserved
 
|-
 
|-
−
| 22 || Undefined
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| 26 || LATTE || IPC_PPC2 (Espresso CPU2)
 
|-
 
|-
−
| 23 || Undefined
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| 27 || ALL || Reserved
 
|-
 
|-
−
| 24 || Undefined
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| 27 || LATTE || IPC_IOP2 (Starbuck CPU2)
 
|-
 
|-
−
| 25 || Undefined
+
| 28 || ALL || {{hw|SATA Controller}} (DBGINT only?)
 
|-
 
|-
−
| 26 || Undefined
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| 28 || LATTE || IPC_PPC1 (Espresso CPU1)
 
|-
 
|-
−
| 27 || Undefined
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| 29 || ALL || Reserved
 
|-
 
|-
−
| 28 || Unknown
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| 29 || LATTE || IPC_IOP1 (Starbuck CPU1)
 
|-
 
|-
−
| 29 || Undefined
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| 30 || ALL || IPCPPC (Espresso in compat mode)
 
|-
 
|-
−
| 30 || {{hw|IPC}} (Espresso)
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| 30 || LATTE || IPC_PPC0 (Espresso CPU0)
 
|-
 
|-
−
| 31 || {{hw|IPC}} (Starbuck)
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| 31 || ALL || IPCIOP (Starbuck in compat mode)
 
|-
 
|-
 +
| 31 || LATTE || IPC_IOP0 (Starbuck CPU0)
 
|}
 
|}
   −
==Register List==
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== Register List ==
−
The Latte IRQ engine has two different register blocks: a global block compatible with the old Wii hardware (Wood), and a new SMP block split across the three Wii U's (Latte) PPC cores and the ARM core. Each core's region of the SMP block has registers equivalent to the old global block.
+
Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for Wood and Latte hardware and another exclusive to Latte hardware.
 +
The subset used for Latte is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.
   −
===Compat block===
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=== Wood block ===
−
{{reglist|Global compat block}}
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{{reglist|Wood block}}
−
{{rla|0x0d800030|32|LT_INTSR_PPC_COMPAT|Triggered IRQs for the PPC in vWii}}
+
{{rla|0x0d800030|32|HW_PPCINTSTS|Triggered IRQs for the PPC core in vWii}}
−
{{rla|0x0d800034|32|LT_INTMR_PPC_COMPAT|Allowed IRQs for the PPC in vWii}}
+
{{rla|0x0d800034|32|HW_PPCINTEN|Allowed IRQs for the PPC core in vWii}}
−
{{rla|0x0d800038|32|LT_INTSR_ARM_COMPAT|Triggered IRQs for the ARM in vWii}}
+
{{rla|0x0d800038|32|HW_IOPINTSTS|Triggered IRQs for the ARM core in vWii}}
−
{{rla|0x0d80003c|32|LT_INTMR_ARM_COMPAT|Allowed IRQs for the ARM in vWii}}
+
{{rla|0x0d80003c|32|HW_IOPIRQINTEN|Allowed IRQs for the ARM core in vWii}}
−
{{rld|0x0d800040|32|LT_INTMR_ARM2x_COMPAT|Unknown}}
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{{rld|0x0d800040|32|HW_IOPFIQINTEN|Allowed FIQs for the ARM core in vWii}}
 
|}
 
|}
   −
===SMP block===
+
=== Latte block ===
−
{{reglist|SMP block - PPC core 0}}
+
{{reglist|Latte block - PPC core 0}}
−
{{rla|0x0d800440|32|LT_INTSR_AHBALL_PPC0|Triggered AHB IRQs for PPC core 0 (all)}}
+
{{rla|0x0d800440|32|LT_PPC0INTSTSALL|Triggered IRQs for PPC core 0 (Wood and Latte)}}
−
{{rla|0x0d800444|32|LT_INTSR_AHBLT_PPC0|Triggered AHB IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d800444|32|LT_PPC0INTSTSLATTE|Triggered IRQs for PPC core 0 (Latte only)}}
−
{{rla|0x0d800448|32|LT_INTMR_AHBALL_PPC0|Allowed AHB IRQs for PPC core 0 (all)}}
+
{{rla|0x0d800448|32|LT_PPC0INTENALL|Allowed IRQs for PPC core 0 (Wood and Latte)}}
−
{{rla|0x0d80044c|32|LT_INTMR_AHBLT_PPC0|Allowed AHB IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d80044c|32|LT_PPC0INTENLATTE|Allowed IRQs for PPC core 0 (Latte only)}}
 
|}
 
|}
   −
{{reglist|SMP block - PPC core 1}}
+
{{reglist|Latte block - PPC core 1}}
−
{{rla|0x0d800450|32|LT_INTSR_AHBALL_PPC1|Triggered AHB IRQs for PPC core 1 (all)}}
+
{{rla|0x0d800450|32|LT_PPC1INTSTSALL|Triggered IRQs for PPC core 1 (Wood and Latte)}}
−
{{rla|0x0d800454|32|LT_INTSR_AHBLT_PPC1|Triggered AHB IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d800454|32|LT_PPC1INTSTSLATTE|Triggered IRQs for PPC core 1 (Latte only)}}
−
{{rla|0x0d800458|32|LT_INTMR_AHBALL_PPC1|Allowed AHB IRQs for PPC core 1 (all)}}
+
{{rla|0x0d800458|32|LT_PPC1INTENALL|Allowed IRQs for PPC core 1 (Wood and Latte)}}
−
{{rla|0x0d80045c|32|LT_INTMR_AHBLT_PPC1|Allowed AHB IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d80045c|32|LT_PPC1INTENLATTE|Allowed IRQs for PPC core 1 (Latte only)}}
 
|}
 
|}
   −
{{reglist|SMP block - PPC core 2}}
+
{{reglist|Latte block - PPC core 2}}
−
{{rla|0x0d800460|32|LT_INTSR_AHBALL_PPC2|Triggered AHB IRQs for PPC core 2 (all)}}
+
{{rla|0x0d800460|32|LT_PPC2INTSTSALL|Triggered IRQs for PPC core 2 (Wood and Latte)}}
−
{{rla|0x0d800464|32|LT_INTSR_AHBLT_PPC2|Triggered AHB IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d800464|32|LT_PPC2INTSTSLATTE|Triggered IRQs for PPC core 2 (Latte only)}}
−
{{rla|0x0d800468|32|LT_INTMR_AHBALL_PPC2|Allowed AHB IRQs for PPC core 2 (all)}}
+
{{rla|0x0d800468|32|LT_PPC2INTENALL|Allowed IRQs for PPC core 2 (Wood and Latte)}}
−
{{rla|0x0d80046c|32|LT_INTMR_AHBLT_PPC2|Allowed AHB IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d80046c|32|LT_PPC2INTENLATTE|Allowed IRQs for PPC core 2 (Latte only)}}
 
|}
 
|}
   −
{{reglist|SMP block - ARM core}}
+
{{reglist|Latte block - ARM core}}
−
{{rla|0x0d800470|32|LT_INTSR_AHBALL_ARM|Triggered AHB IRQs for ARM core (all)}}
+
{{rla|0x0d800470|32|LT_IOPINTSTSALL|Triggered IRQs for ARM core (Wood and Latte)}}
−
{{rla|0x0d800474|32|LT_INTSR_AHBLT_ARM|Triggered AHB IRQs for ARM core (Latte only)}}
+
{{rla|0x0d800474|32|LT_IOPINTSTSLATTE|Triggered IRQs for ARM core (Latte only)}}
−
{{rla|0x0d800478|32|LT_INTMR_AHBALL_ARM|Allowed AHB IRQs for ARM core (all)}}
+
{{rla|0x0d800478|32|LT_IOPIRQINTENALL|Allowed IRQs for ARM core (Wood and Latte)}}
−
{{rla|0x0d80047c|32|LT_INTMR_AHBLT_ARM|Allowed AHB IRQs for ARM core (Latte only)}}
+
{{rla|0x0d80047c|32|LT_IOPIRQINTENLATTE|Allowed IRQs for ARM core (Latte only)}}
−
{{rld|0x0d800480|32|LT_INTMR_AHBALL_ARM2x|Unknown (all)}}
+
{{rld|0x0d800480|32|LT_IOPFIQINTENALL|Allowed FIQs for the ARM core (Wood and Latte)}}
−
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
+
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE|Allowed FIQs for the ARM core (Latte only)}}
 
|}
 
|}
    
== Register descriptions ==
 
== Register descriptions ==
−
{{regsimple|LT_INTSR_AHBALL_PPCx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCxINTSTSALL|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_INTSR_AHBLT_PPCx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCxINTSTSLATTE|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_INTMR_AHBALL_PPCx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+
{{regsimple|LT_PPCxINTENALL|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
−
{{regsimple|LT_INTMR_AHBLT_PPCx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+
{{regsimple|LT_PPCxINTENLATTE|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
−
{{regsimple|LT_INTSR_AHBALL_ARM|addr=0x0d800470|bits=32|access=R/Z}}
+
{{regsimple|LT_IOPINTSTSALL|addr=0x0d800470|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_INTSR_AHBLT_ARM|addr=0x0d800474|bits=32|access=R/Z}}
+
{{regsimple|LT_IOPINTSTSLATTE|addr=0x0d800474|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_INTMR_AHBALL_ARM|addr=0x0d800478|bits=32|access=R/W}}
+
{{regsimple|LT_IOPIRQINTENALL|addr=0x0d800478|bits=32|access=R/W}}
−
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
 
----
 
----
−
{{regsimple|LT_INTMR_AHBLT_ARM|addr=0x0d80047c|bits=32|access=R/W}}
+
{{regsimple|LT_IOPIRQINTENLATTE|addr=0x0d80047c|bits=32|access=R/W}}
−
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
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