339
edits
Changes
→IRQ Sources
Line 8:
Line 8:
Additionally, the (emulated) Hollywood IRQ registers are still available for compat mode (vWii) and debugging.
−|-
−| (1 << 1) || AHBALL || {{hw|NAND Interface}}
There are also traces of additional unused registers which appear to have been used in the past for debugging purposes (ARM2x).
−
The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
−IOSU distinguishes interrupt sources that also existed in the Hollywood chipset (AHBALL) and new sources that are exclusive to the Latte (AHBLT).
+IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LATTE).
−==IRQ Sources==
+== IRQ Sources ==
−{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
+{| class="wikitable"
−|- style="background-color: #ddd;"
+|-
−! IRQ
+! Bit
−! Type
+! Group
! Description
! Description
|-
|-
−| (1 << 0) || AHBALL || Timer (Starbuck)
+| 0 || ALL || TMR (Timer)
−|-
|-
−| (1 << 2) || AHBALL || {{hw|AES Engine}}
+| 0 || LATTE || SD2 ({{hw|SD Host Controller}} for eMMC)
|-
|-
−| (1 << 3) || AHBALL || {{hw|SHA-1 Engine}}
+| 1 || ALL || FLA ({{hw|NAND Interface}})
|-
|-
−| (1 << 4) || AHBALL || {{hw|USB Host Controller}} (EHCI-0)
+| 1 || LATTE || SD3 ({{hw|SD Host Controller}} for Toucan)
|-
|-
−| (1 << 5) || AHBALL || {{hw|USB Host Controller}} (OHCI-0:0)
+| 2 || ALL || AES0 ({{hw|AES Engine}})
|-
|-
−| (1 << 6) || AHBALL || {{hw|USB Host Controller}} (OHCI-0:1)
+| 2 || LATTE || EHCI1 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 7) || AHBALL || {{hw|SD Host Controller}}
+| 3 || ALL || SHA0 ({{hw|SHA-1 Engine}})
|-
|-
−| (1 << 8) || AHBALL || {{hw|802.11 Wireless}}
+| 3 || LATTE || OHCI10 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 9) || AHBALL || Undefined
+| 4 || ALL || EHCI0 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 10) || AHBALL || {{hw|Latte GPIOs}} (Espresso)
+| 4 || LATTE || EHCI2 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 11) || AHBALL || {{hw|Latte GPIOs}} (Starbuck)
+| 5 || ALL || OHCI0 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 12) || AHBALL || SYSPROT
+| 5 || LATTE || OHCI20 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 13) || AHBALL || Undefined
+| 6 || ALL || OHCI1 ({{hw|USB Host Controller}})
|-
|-
−| (1 << 14) || AHBALL || Undefined
+| 6 || LATTE || SATA ({{hw|SATA Controller}})
|-
|-
−| (1 << 15) || AHBALL || Undefined
+| 7 || ALL || SD0 ({{hw|SD Host Controller}})
|-
|-
−| (1 << 16) || AHBALL || Undefined
+| 7 || LATTE || Unknown
|-
|-
−| (1 << 17) || AHBALL || Power button
+| 8 || ALL || SD1 ({{hw|802.11 Wireless}})
|-
|-
−| (1 << 18) || AHBALL || Drive Interface
+| 8 || LATTE || AES1 ({{hw|AES Engine}} for AESS)
|-
|-
−| (1 << 19) || AHBALL || {{hw|USB Host Controller}} (EHCI-1)
+| 9 || ALL || Reserved
|-
|-
−| (1 << 20) || AHBALL || EXI RTC
+| 9 || LATTE || SHA1 ({{hw|SHA-1 Engine}} for SHAS-1)
|-
|-
−| (1 << 21) || AHBALL || Undefined
+| 10 || ALL || GPIPPC ({{hw|Latte GPIOs}} for Espresso)
|-
|-
−| (1 << 22) || AHBALL || Undefined
+| 10 || LATTE || Unknown
|-
|-
−| (1 << 23) || AHBALL || Undefined
+| 11 || ALL || GPIIOP ({{hw|Latte GPIOs}} for Starbuck)
|-
|-
−| (1 << 24) || AHBALL || Undefined
+| 11 || LATTE || GPU7_GC
|-
|-
−| (1 << 25) || AHBALL || Undefined
+| 12 || ALL || DBGINT
|-
|-
−| (1 << 26) || AHBALL || Undefined
+| 12 || LATTE || IOP2X
|-
|-
−| (1 << 27) || AHBALL || Undefined
+| 13 || ALL || VIPIWR
|-
|-
−| (1 << 28) || AHBALL || SATA
+| 13 || LATTE || PRIMARY_I2C (for Espresso)
|-
|-
−| (1 << 29) || AHBALL || Undefined
+| 14 || ALL || SIEMU
|-
|-
−| (1 << 30) || AHBALL || {{hw|IPC}} (Espresso compat)
+| 14 || LATTE || SECONDARY_I2C (for Starbuck)
|-
|-
−| (1 << 31) || AHBALL || {{hw|IPC}} (Starbuck compat)
+| 15 || ALL || SYSRSTB
|-
|-
−| (1 << 0) || AHBLT || {{hw|SD Host Controller}}
+| 15 || LATTE || Reserved
|-
|-
−| (1 << 1) || AHBLT || Unknown
+| 16 || ALL || VIVSYNC
|-
|-
−| (1 << 2) || AHBLT || Unknown
+| 16 || LATTE || Reserved
|-
|-
−| (1 << 3) || AHBLT || Unknown
+| 17 || ALL || Power button
|-
|-
−| (1 << 4) || AHBLT || DRH
+| 17 || LATTE || Reserved
|-
|-
−| (1 << 5) || AHBLT || Unknown
+| 18 || ALL || DI
|-
|-
−| (1 << 6) || AHBLT || Unknown
+| 18 || LATTE || Reserved
|-
|-
−| (1 << 7) || AHBLT || Unknown
+| 19 || ALL || Reserved
|-
|-
−| (1 << 8) || AHBLT || {{hw|AES Engine}} (AESS)
+| 19 || LATTE || Reserved
|-
|-
−| (1 << 9) || AHBLT || {{hw|SHA-1 Engine}} (SHAS-1)
+| 20 || ALL || EXI
|-
|-
−| (1 << 10) || AHBLT || Unknown
+| 20 || LATTE || Reserved
|-
|-
−| (1 << 11) || AHBLT || Unknown
+| 21 || ALL || Reserved
|-
|-
−| (1 << 12) || AHBLT || Unknown
+| 21 || LATTE || Reserved
|-
|-
−| (1 << 13) || AHBLT || I2C (Espresso)
+| 22 || ALL || Reserved
|-
|-
−| (1 << 14) || AHBLT || I2C (Starbuck)
+| 22 || LATTE || Reserved
|-
|-
−| (1 << 15) || AHBLT || Undefined
+| 23 || ALL || Reserved
|-
|-
−| (1 << 16) || AHBLT || Undefined
+| 23 || LATTE || Reserved
|-
|-
−| (1 << 17) || AHBLT || Undefined
+| 24 || ALL || Reserved
|-
|-
−| (1 << 18) || AHBLT || Undefined
+| 24 || LATTE || Reserved
|-
|-
−| (1 << 19) || AHBLT || Undefined
+| 25 || ALL || Reserved
|-
|-
−| (1 << 20) || AHBLT || Undefined
+| 25 || LATTE || Reserved
|-
|-
−| (1 << 21) || AHBLT || Undefined
+| 26 || ALL || Reserved
|-
|-
−| (1 << 22) || AHBLT || Undefined
+| 26 || LATTE || IPC_PPC2 (Espresso CPU2)
|-
|-
−| (1 << 23) || AHBLT || Undefined
+| 27 || ALL || Reserved
|-
|-
−| (1 << 24) || AHBLT || Undefined
+| 27 || LATTE || IPC_IOP2 (Starbuck CPU2)
|-
|-
−| (1 << 25) || AHBLT || Undefined
+| 28 || ALL || {{hw|SATA Controller}} (DBGINT only?)
|-
|-
−| (1 << 26) || AHBLT || {{hw|IPC}} (Espresso CPU2)
+| 28 || LATTE || IPC_PPC1 (Espresso CPU1)
|-
|-
−| (1 << 27) || AHBLT || {{hw|IPC}} (Starbuck CPU2)
+| 29 || ALL || Reserved
|-
|-
−| (1 << 28) || AHBLT || {{hw|IPC}} (Espresso CPU1)
+| 29 || LATTE || IPC_IOP1 (Starbuck CPU1)
|-
|-
−| (1 << 29) || AHBLT || {{hw|IPC}} (Starbuck CPU1)
+| 30 || ALL || IPCPPC (Espresso in compat mode)
|-
|-
−| (1 << 30) || AHBLT || {{hw|IPC}} (Espresso CPU0)
+| 30 || LATTE || IPC_PPC0 (Espresso CPU0)
|-
|-
−| (1 << 31) || AHBLT || {{hw|IPC}} (Starbuck CPU0)
+| 31 || ALL || IPCIOP (Starbuck in compat mode)
|-
|-
+| 31 || LATTE || IPC_IOP0 (Starbuck CPU0)
|}
|}
−==Register List==
+== Register List ==
−Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for compat mode (vWii) and another for normal mode (Wii U).
+Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for Wood and Latte hardware and another exclusive to Latte hardware.
−The subset used for normal mode is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.
+The subset used for Latte is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.
−===Compat block===
+=== Wood block ===
−{{reglist|Global compat block}}
+{{reglist|Wood block}}
−{{rla|0x0d800030|32|LT_INTSR_PPC_COMPAT|Triggered IRQs for the PPC in vWii}}
+{{rla|0x0d800030|32|HW_PPCINTSTS|Triggered IRQs for the PPC core in vWii}}
−{{rla|0x0d800034|32|LT_INTMR_PPC_COMPAT|Allowed IRQs for the PPC in vWii}}
+{{rla|0x0d800034|32|HW_PPCINTEN|Allowed IRQs for the PPC core in vWii}}
−{{rla|0x0d800038|32|LT_INTSR_ARM_COMPAT|Triggered IRQs for the ARM in vWii}}
+{{rla|0x0d800038|32|HW_IOPINTSTS|Triggered IRQs for the ARM core in vWii}}
−{{rla|0x0d80003c|32|LT_INTMR_ARM_COMPAT|Allowed IRQs for the ARM in vWii}}
+{{rla|0x0d80003c|32|HW_IOPIRQINTEN|Allowed IRQs for the ARM core in vWii}}
−{{rld|0x0d800040|32|LT_INTMR_ARM2x_COMPAT|Unknown}}
+{{rld|0x0d800040|32|HW_IOPFIQINTEN|Allowed FIQs for the ARM core in vWii}}
|}
|}
−===SMP block===
+=== Latte block ===
−{{reglist|SMP block - PPC core 0}}
+{{reglist|Latte block - PPC core 0}}
−{{rla|0x0d800440|32|LT_INTSR_AHBALL_PPC0|Triggered AHB IRQs for PPC core 0 (all)}}
+{{rla|0x0d800440|32|LT_PPC0INTSTSALL|Triggered IRQs for PPC core 0 (Wood and Latte)}}
−{{rla|0x0d800444|32|LT_INTSR_AHBLT_PPC0|Triggered AHB IRQs for PPC core 0 (Latte only)}}
+{{rla|0x0d800444|32|LT_PPC0INTSTSLATTE|Triggered IRQs for PPC core 0 (Latte only)}}
−{{rla|0x0d800448|32|LT_INTMR_AHBALL_PPC0|Allowed AHB IRQs for PPC core 0 (all)}}
+{{rla|0x0d800448|32|LT_PPC0INTENALL|Allowed IRQs for PPC core 0 (Wood and Latte)}}
−{{rla|0x0d80044c|32|LT_INTMR_AHBLT_PPC0|Allowed AHB IRQs for PPC core 0 (Latte only)}}
+{{rla|0x0d80044c|32|LT_PPC0INTENLATTE|Allowed IRQs for PPC core 0 (Latte only)}}
|}
|}
−{{reglist|SMP block - PPC core 1}}
+{{reglist|Latte block - PPC core 1}}
−{{rla|0x0d800450|32|LT_INTSR_AHBALL_PPC1|Triggered AHB IRQs for PPC core 1 (all)}}
+{{rla|0x0d800450|32|LT_PPC1INTSTSALL|Triggered IRQs for PPC core 1 (Wood and Latte)}}
−{{rla|0x0d800454|32|LT_INTSR_AHBLT_PPC1|Triggered AHB IRQs for PPC core 1 (Latte only)}}
+{{rla|0x0d800454|32|LT_PPC1INTSTSLATTE|Triggered IRQs for PPC core 1 (Latte only)}}
−{{rla|0x0d800458|32|LT_INTMR_AHBALL_PPC1|Allowed AHB IRQs for PPC core 1 (all)}}
+{{rla|0x0d800458|32|LT_PPC1INTENALL|Allowed IRQs for PPC core 1 (Wood and Latte)}}
−{{rla|0x0d80045c|32|LT_INTMR_AHBLT_PPC1|Allowed AHB IRQs for PPC core 1 (Latte only)}}
+{{rla|0x0d80045c|32|LT_PPC1INTENLATTE|Allowed IRQs for PPC core 1 (Latte only)}}
|}
|}
−{{reglist|SMP block - PPC core 2}}
+{{reglist|Latte block - PPC core 2}}
−{{rla|0x0d800460|32|LT_INTSR_AHBALL_PPC2|Triggered AHB IRQs for PPC core 2 (all)}}
+{{rla|0x0d800460|32|LT_PPC2INTSTSALL|Triggered IRQs for PPC core 2 (Wood and Latte)}}
−{{rla|0x0d800464|32|LT_INTSR_AHBLT_PPC2|Triggered AHB IRQs for PPC core 2 (Latte only)}}
+{{rla|0x0d800464|32|LT_PPC2INTSTSLATTE|Triggered IRQs for PPC core 2 (Latte only)}}
−{{rla|0x0d800468|32|LT_INTMR_AHBALL_PPC2|Allowed AHB IRQs for PPC core 2 (all)}}
+{{rla|0x0d800468|32|LT_PPC2INTENALL|Allowed IRQs for PPC core 2 (Wood and Latte)}}
−{{rla|0x0d80046c|32|LT_INTMR_AHBLT_PPC2|Allowed AHB IRQs for PPC core 2 (Latte only)}}
+{{rla|0x0d80046c|32|LT_PPC2INTENLATTE|Allowed IRQs for PPC core 2 (Latte only)}}
|}
|}
−{{reglist|SMP block - ARM core}}
+{{reglist|Latte block - ARM core}}
−{{rla|0x0d800470|32|LT_INTSR_AHBALL_ARM|Triggered AHB IRQs for ARM core (all)}}
+{{rla|0x0d800470|32|LT_IOPINTSTSALL|Triggered IRQs for ARM core (Wood and Latte)}}
−{{rla|0x0d800474|32|LT_INTSR_AHBLT_ARM|Triggered AHB IRQs for ARM core (Latte only)}}
+{{rla|0x0d800474|32|LT_IOPINTSTSLATTE|Triggered IRQs for ARM core (Latte only)}}
−{{rla|0x0d800478|32|LT_INTMR_AHBALL_ARM|Allowed AHB IRQs for ARM core (all)}}
+{{rla|0x0d800478|32|LT_IOPIRQINTENALL|Allowed IRQs for ARM core (Wood and Latte)}}
−{{rla|0x0d80047c|32|LT_INTMR_AHBLT_ARM|Allowed AHB IRQs for ARM core (Latte only)}}
+{{rla|0x0d80047c|32|LT_IOPIRQINTENLATTE|Allowed IRQs for ARM core (Latte only)}}
−{{rld|0x0d800480|32|LT_INTMR_AHBALL_ARM2x|Unknown (all)}}
+{{rld|0x0d800480|32|LT_IOPFIQINTENALL|Allowed FIQs for the ARM core (Wood and Latte)}}
−{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
+{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE|Allowed FIQs for the ARM core (Latte only)}}
|}
|}
== Register descriptions ==
== Register descriptions ==
−{{regsimple|LT_INTSR_AHBALL_PPCx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+{{regsimple|LT_PPCxINTSTSALL|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_INTSR_AHBLT_PPCx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+{{regsimple|LT_PPCxINTSTSLATTE|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_INTMR_AHBALL_PPCx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+{{regsimple|LT_PPCxINTENALL|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
----
----
−{{regsimple|LT_INTMR_AHBLT_PPCx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+{{regsimple|LT_PPCxINTENLATTE|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
----
----
−{{regsimple|LT_INTSR_AHBALL_ARM|addr=0x0d800470|bits=32|access=R/Z}}
+{{regsimple|LT_IOPINTSTSALL|addr=0x0d800470|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_INTSR_AHBLT_ARM|addr=0x0d800474|bits=32|access=R/Z}}
+{{regsimple|LT_IOPINTSTSLATTE|addr=0x0d800474|bits=32|access=R/Z}}
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
----
----
−{{regsimple|LT_INTMR_AHBALL_ARM|addr=0x0d800478|bits=32|access=R/W}}
+{{regsimple|LT_IOPIRQINTENALL|addr=0x0d800478|bits=32|access=R/W}}
−This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
----
----
−{{regsimple|LT_INTMR_AHBLT_ARM|addr=0x0d80047c|bits=32|access=R/W}}
+{{regsimple|LT_IOPIRQINTENLATTE|addr=0x0d80047c|bits=32|access=R/W}}
−This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.