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Hardware/Latte IRQs (view source)

Revision as of 00:56, 27 November 2023

183 bytes added ,  00:56, 27 November 2023
→‎IRQ Sources
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The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
 
The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both.
−
IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LT).
+
IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LATTE).
    
== IRQ Sources ==
 
== IRQ Sources ==
−
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
+
{| class="wikitable"
−
|- style="background-color: #ddd;"
+
|-
−
! IRQ
+
! Bit
 
! Group
 
! Group
 
! Description
 
! Description
 
|-
 
|-
−
| 0 || ALL || Timer (Starbuck)
+
| 0 || ALL || TMR (Timer)
−
|-
  −
| 1 || ALL || {{hw|NAND Interface}}
   
|-
 
|-
−
| 2 || ALL || {{hw|AES Engine}}
+
| 0 || LATTE || SD2 ({{hw|SD Host Controller}} for eMMC)
 
|-
 
|-
−
| 3 || ALL || {{hw|SHA-1 Engine}}
+
| 1 || ALL || FLA ({{hw|NAND Interface}})
 
|-
 
|-
−
| 4 || ALL || {{hw|USB Host Controller}} (EHCI-0)
+
| 1 || LATTE || SD3 ({{hw|SD Host Controller}} for Toucan)
 
|-
 
|-
−
| 5 || ALL || {{hw|USB Host Controller}} (OHCI-0:0)
+
| 2 || ALL || AES0 ({{hw|AES Engine}})
 
|-
 
|-
−
| 6 || ALL || {{hw|USB Host Controller}} (OHCI-0:1)
+
| 2 || LATTE || EHCI1 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 7 || ALL || {{hw|SD Host Controller}}
+
| 3 || ALL || SHA0 ({{hw|SHA-1 Engine}})
 
|-
 
|-
−
| 8 || ALL || {{hw|802.11 Wireless}}
+
| 3 || LATTE || OHCI10 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 9 || ALL || Undefined
+
| 4 || ALL || EHCI0 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 10 || ALL || {{hw|Latte GPIOs}} (Espresso)
+
| 4 || LATTE || EHCI2 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 11 || ALL || {{hw|Latte GPIOs}} (Starbuck)
+
| 5 || ALL || OHCI0 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 12 || ALL || SYSPROT
+
| 5 || LATTE || OHCI20 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 13 || ALL || Undefined
+
| 6 || ALL || OHCI1 ({{hw|USB Host Controller}})
 
|-
 
|-
−
| 14 || ALL || Undefined
+
| 6 || LATTE || SATA ({{hw|SATA Controller}})
 
|-
 
|-
−
| 15 || ALL || Undefined
+
| 7 || ALL || SD0 ({{hw|SD Host Controller}})
 
|-
 
|-
−
| 16 || ALL || {{hw|USB Host Controller}} (EHCI-1)
+
| 7 || LATTE || Unknown
 
|-
 
|-
−
| 17 || ALL || Power button
+
| 8 || ALL || SD1 ({{hw|802.11 Wireless}})
 
|-
 
|-
−
| 18 || ALL || Drive Interface
+
| 8 || LATTE || AES1 ({{hw|AES Engine}} for AESS)
 
|-
 
|-
−
| 19 || ALL || Undefined
+
| 9 || ALL || Reserved
 
|-
 
|-
−
| 20 || ALL || EXI RTC
+
| 9 || LATTE || SHA1 ({{hw|SHA-1 Engine}} for SHAS-1)
 
|-
 
|-
−
| 21 || ALL || Undefined
+
| 10 || ALL || GPIPPC ({{hw|Latte GPIOs}} for Espresso)
 
|-
 
|-
−
| 22 || ALL || Undefined
+
| 10 || LATTE || Unknown
 
|-
 
|-
−
| 23 || ALL || Undefined
+
| 11 || ALL || GPIIOP ({{hw|Latte GPIOs}} for Starbuck)
 
|-
 
|-
−
| 24 || ALL || Undefined
+
| 11 || LATTE || GPU7_GC
 
|-
 
|-
−
| 25 || ALL || Undefined
+
| 12 || ALL || DBGINT
 
|-
 
|-
−
| 26 || ALL || Undefined
+
| 12 || LATTE || IOP2X
 
|-
 
|-
−
| 27 || ALL || Undefined
+
| 13 || ALL || VIPIWR
 
|-
 
|-
−
| 28 || ALL || SATA
+
| 13 || LATTE || PRIMARY_I2C (for Espresso)
 
|-
 
|-
−
| 29 || ALL || Undefined
+
| 14 || ALL || SIEMU
 
|-
 
|-
−
| 30 || ALL || {{hw|IPC}} (Espresso compat)
+
| 14 || LATTE || SECONDARY_I2C (for Starbuck)
 
|-
 
|-
−
| 31 || ALL || {{hw|IPC}} (Starbuck compat)
+
| 15 || ALL || SYSRSTB
 
|-
 
|-
−
| 0 || LT || {{hw|SD Host Controller}}
+
| 15 || LATTE || Reserved
 
|-
 
|-
−
| 1 || LT || Unknown
+
| 16 || ALL || VIVSYNC
 
|-
 
|-
−
| 2 || LT || Unknown
+
| 16 || LATTE || Reserved
 
|-
 
|-
−
| 3 || LT || {{hw|USB Host Controller}} (OHCI-1:0)
+
| 17 || ALL || Power button
 
|-
 
|-
−
| 4 || LT || {{hw|USB Host Controller}} (EHCI-2)
+
| 17 || LATTE || Reserved
 
|-
 
|-
−
| 5 || LT || {{hw|USB Host Controller}} (OHCI-2:0)
+
| 18 || ALL || DI
 
|-
 
|-
−
| 6 || LT || Unknown
+
| 18 || LATTE || Reserved
 
|-
 
|-
−
| 7 || LT || Unknown
+
| 19 || ALL || Reserved
 
|-
 
|-
−
| 8 || LT || {{hw|AES Engine}} (AESS)
+
| 19 || LATTE || Reserved
 
|-
 
|-
−
| 9 || LT || {{hw|SHA-1 Engine}} (SHAS-1)
+
| 20 || ALL || EXI
 
|-
 
|-
−
| 10 || LT || Unknown
+
| 20 || LATTE || Reserved
 
|-
 
|-
−
| 11 || LT || Unknown
+
| 21 || ALL || Reserved
 
|-
 
|-
−
| 12 || LT || Unknown
+
| 21 || LATTE || Reserved
 
|-
 
|-
−
| 13 || LT || I2C (Espresso)
+
| 22 || ALL || Reserved
 
|-
 
|-
−
| 14 || LT || I2C (Starbuck)
+
| 22 || LATTE || Reserved
 
|-
 
|-
−
| 15 || LT || Undefined
+
| 23 || ALL || Reserved
 
|-
 
|-
−
| 16 || LT || Undefined
+
| 23 || LATTE || Reserved
 
|-
 
|-
−
| 17 || LT || Undefined
+
| 24 || ALL || Reserved
 
|-
 
|-
−
| 18 || LT || Undefined
+
| 24 || LATTE || Reserved
 
|-
 
|-
−
| 19 || LT || Undefined
+
| 25 || ALL || Reserved
 
|-
 
|-
−
| 20 || LT || Undefined
+
| 25 || LATTE || Reserved
 
|-
 
|-
−
| 21 || LT || Undefined
+
| 26 || ALL || Reserved
 
|-
 
|-
−
| 22 || LT || Undefined
+
| 26 || LATTE || IPC_PPC2 (Espresso CPU2)
 
|-
 
|-
−
| 23 || LT || Undefined
+
| 27 || ALL || Reserved
 
|-
 
|-
−
| 24 || LT || Undefined
+
| 27 || LATTE || IPC_IOP2 (Starbuck CPU2)
 
|-
 
|-
−
| 25 || LT || Undefined
+
| 28 || ALL || {{hw|SATA Controller}} (DBGINT only?)
 
|-
 
|-
−
| 26 || LT || {{hw|IPC}} (Espresso CPU2)
+
| 28 || LATTE || IPC_PPC1 (Espresso CPU1)
 
|-
 
|-
−
| 27 || LT || {{hw|IPC}} (Starbuck CPU2)
+
| 29 || ALL || Reserved
 
|-
 
|-
−
| 28 || LT || {{hw|IPC}} (Espresso CPU1)
+
| 29 || LATTE || IPC_IOP1 (Starbuck CPU1)
 
|-
 
|-
−
| 29 || LT || {{hw|IPC}} (Starbuck CPU1)
+
| 30 || ALL || IPCPPC (Espresso in compat mode)
 
|-
 
|-
−
| 30 || LT || {{hw|IPC}} (Espresso CPU0)
+
| 30 || LATTE || IPC_PPC0 (Espresso CPU0)
 
|-
 
|-
−
| 31 || LT || {{hw|IPC}} (Starbuck CPU0)
+
| 31 || ALL || IPCIOP (Starbuck in compat mode)
 
|-
 
|-
 +
| 31 || LATTE || IPC_IOP0 (Starbuck CPU0)
 
|}
 
|}
   Line 153: Line 152:  
=== Wood block ===
 
=== Wood block ===
 
{{reglist|Wood block}}
 
{{reglist|Wood block}}
−
{{rla|0x0d800030|32|HW_PPCIRQFLAG|Triggered IRQs for the PPC core in vWii}}
+
{{rla|0x0d800030|32|HW_PPCINTSTS|Triggered IRQs for the PPC core in vWii}}
−
{{rla|0x0d800034|32|HW_PPCIRQMASK|Allowed IRQs for the PPC core in vWii}}
+
{{rla|0x0d800034|32|HW_PPCINTEN|Allowed IRQs for the PPC core in vWii}}
−
{{rla|0x0d800038|32|HW_ARMIRQFLAG|Triggered IRQs for the ARM core in vWii}}
+
{{rla|0x0d800038|32|HW_IOPINTSTS|Triggered IRQs for the ARM core in vWii}}
−
{{rla|0x0d80003c|32|HW_ARMIRQMASK|Allowed IRQs for the ARM core in vWii}}
+
{{rla|0x0d80003c|32|HW_IOPIRQINTEN|Allowed IRQs for the ARM core in vWii}}
−
{{rld|0x0d800040|32|HW_ARMFIQMASK|Allowed FIQs for the ARM core in vWii}}
+
{{rld|0x0d800040|32|HW_IOPFIQINTEN|Allowed FIQs for the ARM core in vWii}}
 
|}
 
|}
    
=== Latte block ===
 
=== Latte block ===
 
{{reglist|Latte block - PPC core 0}}
 
{{reglist|Latte block - PPC core 0}}
−
{{rla|0x0d800440|32|LT_PPCIRQFLAGALL0|Triggered IRQs for PPC core 0 (all)}}
+
{{rla|0x0d800440|32|LT_PPC0INTSTSALL|Triggered IRQs for PPC core 0 (Wood and Latte)}}
−
{{rla|0x0d800444|32|LT_PPCIRQFLAGLT0|Triggered IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d800444|32|LT_PPC0INTSTSLATTE|Triggered IRQs for PPC core 0 (Latte only)}}
−
{{rla|0x0d800448|32|LT_PPCIRQMASKALL0|Allowed IRQs for PPC core 0 (all)}}
+
{{rla|0x0d800448|32|LT_PPC0INTENALL|Allowed IRQs for PPC core 0 (Wood and Latte)}}
−
{{rla|0x0d80044c|32|LT_PPCIRQMASKLT0|Allowed IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d80044c|32|LT_PPC0INTENLATTE|Allowed IRQs for PPC core 0 (Latte only)}}
 
|}
 
|}
    
{{reglist|Latte block - PPC core 1}}
 
{{reglist|Latte block - PPC core 1}}
−
{{rla|0x0d800450|32|LT_PPCIRQFLAGALL1|Triggered IRQs for PPC core 1 (all)}}
+
{{rla|0x0d800450|32|LT_PPC1INTSTSALL|Triggered IRQs for PPC core 1 (Wood and Latte)}}
−
{{rla|0x0d800454|32|LT_PPCIRQFLAGLT1|Triggered IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d800454|32|LT_PPC1INTSTSLATTE|Triggered IRQs for PPC core 1 (Latte only)}}
−
{{rla|0x0d800458|32|LT_PPCIRQMASKALL1|Allowed IRQs for PPC core 1 (all)}}
+
{{rla|0x0d800458|32|LT_PPC1INTENALL|Allowed IRQs for PPC core 1 (Wood and Latte)}}
−
{{rla|0x0d80045c|32|LT_PPCIRQMASKLT1|Allowed IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d80045c|32|LT_PPC1INTENLATTE|Allowed IRQs for PPC core 1 (Latte only)}}
 
|}
 
|}
    
{{reglist|Latte block - PPC core 2}}
 
{{reglist|Latte block - PPC core 2}}
−
{{rla|0x0d800460|32|LT_PPCIRQFLAGALL2|Triggered IRQs for PPC core 2 (all)}}
+
{{rla|0x0d800460|32|LT_PPC2INTSTSALL|Triggered IRQs for PPC core 2 (Wood and Latte)}}
−
{{rla|0x0d800464|32|LT_PPCIRQFLAGLT2|Triggered IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d800464|32|LT_PPC2INTSTSLATTE|Triggered IRQs for PPC core 2 (Latte only)}}
−
{{rla|0x0d800468|32|LT_PPCIRQMASKALL2|Allowed IRQs for PPC core 2 (all)}}
+
{{rla|0x0d800468|32|LT_PPC2INTENALL|Allowed IRQs for PPC core 2 (Wood and Latte)}}
−
{{rla|0x0d80046c|32|LT_PPCIRQMASKLT2|Allowed IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d80046c|32|LT_PPC2INTENLATTE|Allowed IRQs for PPC core 2 (Latte only)}}
 
|}
 
|}
    
{{reglist|Latte block - ARM core}}
 
{{reglist|Latte block - ARM core}}
−
{{rla|0x0d800470|32|LT_ARMIRQFLAGALL|Triggered IRQs for ARM core (all)}}
+
{{rla|0x0d800470|32|LT_IOPINTSTSALL|Triggered IRQs for ARM core (Wood and Latte)}}
−
{{rla|0x0d800474|32|LT_ARMIRQFLAGLT|Triggered IRQs for ARM core (Latte only)}}
+
{{rla|0x0d800474|32|LT_IOPINTSTSLATTE|Triggered IRQs for ARM core (Latte only)}}
−
{{rla|0x0d800478|32|LT_ARMIRQMASKALL|Allowed IRQs for ARM core (all)}}
+
{{rla|0x0d800478|32|LT_IOPIRQINTENALL|Allowed IRQs for ARM core (Wood and Latte)}}
−
{{rla|0x0d80047c|32|LT_ARMIRQMASKLT|Allowed IRQs for ARM core (Latte only)}}
+
{{rla|0x0d80047c|32|LT_IOPIRQINTENLATTE|Allowed IRQs for ARM core (Latte only)}}
−
{{rld|0x0d800480|32|LT_ARMFIQMASKALL|Allowed FIQs for the ARM core (all)}}
+
{{rld|0x0d800480|32|LT_IOPFIQINTENALL|Allowed FIQs for the ARM core (Wood and Latte)}}
−
{{rld|0x0d800484|32|LT_ARMFIQMASKLT|Allowed FIQs for the ARM core (Latte only)}}
+
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE|Allowed FIQs for the ARM core (Latte only)}}
 
|}
 
|}
    
== Register descriptions ==
 
== Register descriptions ==
−
{{regsimple|LT_PPCIRQFLAGALLx|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCxINTSTSALL|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_PPCIRQFLAGLTx|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCxINTSTSLATTE|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_PPCIRQMASKALLx|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+
{{regsimple|LT_PPCxINTENALL|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
−
{{regsimple|LT_PPCIRQMASKLTx|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+
{{regsimple|LT_PPCxINTENLATTE|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
−
{{regsimple|LT_ARMIRQFLAGALL|addr=0x0d800470|bits=32|access=R/Z}}
+
{{regsimple|LT_IOPINTSTSALL|addr=0x0d800470|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_ARMIRQFLAGLT|addr=0x0d800474|bits=32|access=R/Z}}
+
{{regsimple|LT_IOPINTSTSLATTE|addr=0x0d800474|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_ARMIRQMASKALL|addr=0x0d800478|bits=32|access=R/W}}
+
{{regsimple|LT_IOPIRQINTENALL|addr=0x0d800478|bits=32|access=R/W}}
−
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
 
----
 
----
−
{{regsimple|LT_ARMIRQMASKLT|addr=0x0d80047c|bits=32|access=R/W}}
+
{{regsimple|LT_IOPIRQINTENLATTE|addr=0x0d80047c|bits=32|access=R/W}}
−
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the ARM IRQ to be asserted.
+
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
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