In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Difference between revisions of "Hardware/AHM controller"

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m (Hexkyz moved page Hardware/XN controller to Hardware/AHM controller: Correct name)
m (Hexkyz moved page Hardware/AHMN controller to Hardware/AHM controller over redirect)
 
(3 intermediate revisions by the same user not shown)
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 +
= AHM =
 
{{Infobox MMIO
 
{{Infobox MMIO
 +
| title = AHM controller
 +
| arm = Full
 +
| base = 0x0d8b0000
 +
| len = 0x800
 +
| bits = 32
 +
| ppcirq = ???
 +
| latteirq = ???
 +
}}
 +
 +
AHM (short for AHB_MEM) is a custom bridge responsible for connecting the AHB bus to the [[Hardware/Memory Controller|Memory Controller]].
 +
 +
== Register List ==
 +
{{reglist|AHM controller}}
 +
{{rld|0x0d8b0000|32|AHM_SECDDR|AHM DDR memory security}}
 +
{{rld|0x0d8b0004|32|AHM_SECSPL|AHM SPLASH memory security}}
 +
{{rld|0x0d8b0008|32|AHM_RDBI|AHM read data buffer invalidate mask}}
 +
{{rld|0x0d8b0010|32|AHM_PREFCFG|AHM prefetch configuration}}
 +
{{rld|0x0d8b0020|32|AHM_INTMSK|AHM interrupt mask}}
 +
{{rld|0x0d8b0030|32|AHM_INTSTS|AHM interrupt status}}
 +
{{rld|0x0d8b0040|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8b0044|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8b0100...0x0d8b0300|32|AHM_PROTDDR|Each register controls access protection for one page of DDR memory (page size depends on AHM_SECDDR)}}
 +
{{rld|0x0d8b0500...0x0d8b0700|32|AHM_PROTSPL|Each register controls access protection for one page of SPLASH memory (page size depends on AHM_SECSPL)}}
 +
|}
 +
 +
== Register Details ==
 +
 +
= AHMN =
 +
The Latte hardware contains an enhanced version of AHB_MEM dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).
 +
 +
{{Infobox MMIO
 +
| title = AHMN controller
 
| arm = Full
 
| arm = Full
 
| base = 0x0d8b0800
 
| base = 0x0d8b0800
Line 7: Line 40:
 
| latteirq = ???
 
| latteirq = ???
 
}}
 
}}
−
 
−
Similarly to the [[Hardware/Memory_Controller|memory controller]] block connected to the AHB, the Latte hardware implements a customized XN (eXecute Never) controller to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).<br>
 
−
This controller is named AHMN (AHB memory XN?) by the IOSU.
 
  
 
== Register List ==
 
== Register List ==
−
{{reglist|XN Controller}}
+
{{reglist|AHMN controller}}
−
{{rld|0x0d8b0800|32|AHMN_CFGMEM0|AHMN configuration for MEM0 protection}}
+
{{rld|0x0d8b0800|32|AHMN_SECMEM0|AHMN MEM0 memory security}}
−
{{rld|0x0d8b0804|32|AHMN_CFGMEM1|AHMN configuration for MEM1 protection}}
+
{{rld|0x0d8b0804|32|AHMN_SECMEM1|AHMN MEM1 memory security}}
−
{{rld|0x0d8b0808|32|AHMN_CFGMEM2|AHMN configuration for MEM2 protection}}
+
{{rld|0x0d8b0808|32|AHMN_SECMEM2|AHMN MEM2 memory security}}
−
{{rld|0x0d8b080c|32|AHMN_RDBIMSK|AHMN read buffer invalidate mask}}
+
{{rld|0x0d8b080c|32|AHMN_RDBI|AHMN read data buffer invalidate mask}}
 
{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}
 
{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}
 
{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}
 
{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}
−
{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}
+
{{rld|0x0d8b0840|32|UNKNOWN|Unknown}}
−
{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}
+
{{rld|0x0d8b0844|32|UNKNOWN|Unknown}}
−
{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN read/write transfer status}}
+
{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN transfer status}}
 
{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}
 
{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}
−
{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}
+
{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_PROTMEM0|Each register controls access protection for one page of MEM0 memory (page size depends on AHMN_SECMEM0)}}
−
{{rld|0x0d8b0a00...0x0d8b0c00|32|AHMN_MEM1|Each register represents one block of MEM1 memory (block size depends on the AHMN configuration for MEM1)}}
+
{{rld|0x0d8b0a00...0x0d8b0c00|32|AHMN_PROTMEM1|Each register controls access protection for one page of MEM1 memory (page size depends on AHMN_SECMEM1)}}
−
{{rld|0x0d8b0c00...0x0d8b1000|32|AHMN_MEM2|Each register represents one block of MEM2 memory (block size depends on the AHMN configuration for MEM2)}}
+
{{rld|0x0d8b0c00...0x0d8b1000|32|AHMN_PROTMEM2|Each register controls access protection for one page of MEM2 memory (page size depends on AHMN_SECMEM2)}}
 
|}
 
|}
  
 
== Register Details ==
 
== Register Details ==

Latest revision as of 17:29, 31 December 2024

AHM

AHM controller
Access
EspressoNone
StarbuckFull
Registers
Base0x0d8b0000
Length0x800
Access size32 bits
Byte orderBig Endian
IRQs
Espresso???
Latte???
This box: view • talk • edit

AHM (short for AHB_MEM) is a custom bridge responsible for connecting the AHB bus to the Memory Controller.

Register List

AHM controller
Address Bits Name Description
0x0d8b0000 32 AHM_SECDDR AHM DDR memory security
0x0d8b0004 32 AHM_SECSPL AHM SPLASH memory security
0x0d8b0008 32 AHM_RDBI AHM read data buffer invalidate mask
0x0d8b0010 32 AHM_PREFCFG AHM prefetch configuration
0x0d8b0020 32 AHM_INTMSK AHM interrupt mask
0x0d8b0030 32 AHM_INTSTS AHM interrupt status
0x0d8b0040 32 UNKNOWN Unknown
0x0d8b0044 32 UNKNOWN Unknown
0x0d8b0100...0x0d8b0300 32 AHM_PROTDDR Each register controls access protection for one page of DDR memory (page size depends on AHM_SECDDR)
0x0d8b0500...0x0d8b0700 32 AHM_PROTSPL Each register controls access protection for one page of SPLASH memory (page size depends on AHM_SECSPL)

Register Details

AHMN

The Latte hardware contains an enhanced version of AHB_MEM dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).

AHMN controller
Access
EspressoNone
StarbuckFull
Registers
Base0x0d8b0800
Length0x800
Access size32 bits
Byte orderBig Endian
IRQs
Espresso???
Latte???
This box: view • talk • edit

Register List

AHMN controller
Address Bits Name Description
0x0d8b0800 32 AHMN_SECMEM0 AHMN MEM0 memory security
0x0d8b0804 32 AHMN_SECMEM1 AHMN MEM1 memory security
0x0d8b0808 32 AHMN_SECMEM2 AHMN MEM2 memory security
0x0d8b080c 32 AHMN_RDBI AHMN read data buffer invalidate mask
0x0d8b0820 32 AHMN_INTMSK AHMN interrupt mask
0x0d8b0824 32 AHMN_INTSTS AHMN interrupt status
0x0d8b0840 32 UNKNOWN Unknown
0x0d8b0844 32 UNKNOWN Unknown
0x0d8b0850 32 AHMN_TRFSTS AHMN transfer status
0x0d8b0854 32 AHMN_WORKAROUND Unknown
0x0d8b0900...0x0d8b0980 32 AHMN_PROTMEM0 Each register controls access protection for one page of MEM0 memory (page size depends on AHMN_SECMEM0)
0x0d8b0a00...0x0d8b0c00 32 AHMN_PROTMEM1 Each register controls access protection for one page of MEM1 memory (page size depends on AHMN_SECMEM1)
0x0d8b0c00...0x0d8b1000 32 AHMN_PROTMEM2 Each register controls access protection for one page of MEM2 memory (page size depends on AHMN_SECMEM2)

Register Details

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