In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

Hardware/Latte GPIOs: Difference between revisions

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The Latte chipset includes two groups of general purpose I/O lines with interrupt capability: one common to Wood and Latte hardware (ALL) and another exclusively available to Latte (LT). Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.
The Latte chipset includes two groups of general purpose I/O lines with interrupt capability: one common to Wood and Latte hardware (ALL) and another exclusively available to Latte (LATTE). Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.


== Pin connections ==
== Pins ==
{| class="wikitable"
{| class="wikitable"
|-  
|-  
Line 18: Line 18:
! Group
! Group
! Direction
! Direction
! Connection
! Description
! Description
|-
|-
| 0 || ALL || IN || RTCSysInt || Power button input.
| 0 || ALL || IN || RtcSysInt
|-
|-
| 0 || LT || OUT || FanSpeed || Fan speed.
| 0 || LATTE || OUT || FanSpeed
|-
|-
| 0 || ALL || I/O || ToucanSelect || "Toucan" select (devkit only).
| 1 || ALL || OUT || DwifiMode
|-
|-
| 1 || ALL || OUT || DWiFiMode || DWiFi mode.
| 1 || LATTE || IN || SmcScl
|-
|-
| 1 || LT || IN || SMCI2CClock || SMC (surface mounted components) I²C Clock.
| 2 || ALL || OUT || FanPower
|-
|-
| 2 || ALL || OUT || FanPower || Fan power, active high.
| 2 || LATTE || IN || SmcSda
|-
|-
| 2 || LT || IN || SMCI2CData || SMC (surface mounted components) I²C Data.
| 3 || ALL || OUT || DcdcPowerControl (active high) or CcrhIo3 (Evaluation or Cortado boards only)
|-
|-
| 3 || ALL || OUT || DCDCPwrCnt || DC/DC converter power, active high.
| 3 || LATTE || OUT || DcdcPowerControl2 (active high)
|-
|-
| 3 || LT || OUT || DCDCPwrCnt2 || DC/DC converter power, active high.
| 4 || ALL || OUT || NC (not connected) or DISpinUp (Cortado boards only)
|-
|-
| 3 || ALL || OUT || CCRIO3 || Unknown (duplicate?)
| 4 || LATTE || IN || AvInt (A/V encoder interrupt from Espresso)
|-
|-
| 4 || ALL || UNK || UNKNOWN || Unknown.
| 5 || ALL || OUT || Esp10Workaround or SlotLED (Cortado boards only)
|-
|-
| 4 || LT || IN || AVInterrupt || A/V encoder interrupt (from Espresso).
| 5 || LATTE || OUT || CcrhIo12 or CCRHFWCtrl (Cortado boards only)
|-
|-
| 5 || ALL || OUT || ESP10WorkAround || Unknown.
| 6 || ALL || OUT || DRCPWRREQ
|-
|-
| 5 || LT || OUT || CCRIO12 || Unknown.
| 6 || LATTE || OUT || AvReset (A/V encoder reset from Espresso)
|-
|-
| 6 || ALL || UNK || UNKNOWN || Unknown.
| 7 || ALL || IN || JIG
|-
|-
| 6 || LT || OUT || AVReset || A/V encoder reset (from Espresso).
| 7 || LATTE || NONE || Reserved
|-
|-
| 7 || ALL || UNK || UNKNOWN || Unknown.
| 8 || ALL || OUT || PadPd (GamePad power state)
|-
|-
| 8 || ALL || OUT || PADPD || Gamepad power state.
| 8 || LATTE || NONE || Reserved
|-
|-
| 9 || ALL || UNK || UNKNOWN  || Unknown.
| 9 || ALL || I/O || ToucanSelect (devkit only)
|-
|-
| 10 || ALL || OUT || EEPROM_CS || SEEPROM Chip Select.
| 9 || LATTE || NONE || Reserved
|-
|-
| 11 || ALL || OUT || EEPROM_SK || SEEPROM Clock.
| 10 || ALL || OUT || EepromCs (EEPROM chip select)
|-
|-
| 12 || ALL || OUT || EEPROM_DO || Data to SEEPROM.
| 10 || LATTE || NONE || Reserved
|-
|-
| 13 || ALL || IN || EEPROM_DI || Data from SEEPROM.
| 11 || ALL || OUT || EepromSk (EEPROM clock)
|-
|-
| 14 || ALL || OUT || AV0I2CClock || A/V Encoder (#0) I²C Clock.
| 11 || LATTE || NONE || Reserved
|-
|-
| 15 || ALL || OUT || AV0I2CData || A/V Encoder (#0) I²C Data.
| 12 || ALL || OUT || EepromDo (data to EEPROM)
|-
|-
| 16 || ALL || I/O || NDEV_LED || Development unit's LED (devkit only).
| 12 || LATTE || NONE || Reserved
|-
|-
| 16 || ALL || OUT || DEBUG0 || Debug Testpoint (TP50).
| 13 || ALL || IN || EepromDi (data from EEPROM)
|-
|-
| 17 || ALL || OUT || DEBUG1 || Debug Testpoint (TP51).
| 13 || LATTE || NONE || Reserved
|-
|-
| 18 || ALL || OUT || DEBUG2 || Debug Testpoint (TP52).
| 14 || ALL || OUT || Av0I2cClock (A/V Encoder 4IN1 I²C Clock)
|-
|-
| 19 || ALL || OUT || DEBUG3 || Debug Testpoint (TP53).
| 14 || LATTE || NONE || Reserved
|-
|-
| 20 || ALL || OUT || DEBUG4 || Debug Testpoint (TP55).
| 15 || ALL || OUT || Av0I2cData (A/V Encoder 4IN1 I²C Data)
|-
|-
| 21 || ALL || OUT || DEBUG5 || Debug Testpoint (TP54).
| 15 || LATTE || NONE || Reserved
|-
|-
| 22 || ALL || OUT || DEBUG6 || Debug Testpoint (TP48).
| 16 || ALL || OUT || NdevLed0 (devkit only, debug testpoint TP50)
|-
|-
| 23 || ALL || OUT || DEBUG7 || Debug Testpoint (TP49).
| 16 || LATTE || NONE || Reserved
|-
|-
| 24 || ALL || OUT || AV1I2CClock || A/V Encoder (#1) I²C Clock.
| 17 || ALL || OUT || NdevLed1 (devkit only, debug testpoint TP51)
|-
|-
| 25 || ALL || OUT || AV1I2CData || A/V Encoder (#1) I²C Data.
| 17 || LATTE || NONE || Reserved
|-
|-
| 26 || ALL || OUT || MuteLamp || Unknown.
| 18 || ALL || OUT || NdevLed2 (devkit only, debug testpoint TP52)
|-
|-
| 27 || ALL || OUT || BlueToothMode || BlueTooth mode.
| 18 || LATTE || NONE || Reserved
|-
|-
| 28 || ALL || OUT || CCRHReset || CCR (constant current regulator?) hard reset.
| 19 || ALL || OUT || NdevLed3 (devkit only, debug testpoint TP53)
|-
|-
| 29 || ALL || OUT || WiFiMode || WiFi mode.
| 19 || LATTE || NONE || Reserved
|-
|-
| 30 || ALL || OUT || SDC0S0Power || SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD card.
| 20 || ALL || OUT || NdevLed4 (devkit only, debug testpoint TP55)
|-
| 20 || LATTE || NONE || Reserved
|-
| 21 || ALL || OUT || NdevLed5 (devkit only, debug testpoint TP54)
|-
| 21 || LATTE || NONE || Reserved
|-
| 22 || ALL || OUT || NdevLed6 (devkit only, debug testpoint TP48)
|-
| 22 || LATTE || NONE || Reserved
|-
| 23 || ALL || OUT || NdevLed7 (devkit only, debug testpoint TP49)
|-
| 23 || LATTE || NONE || Reserved
|-
| 24 || ALL || OUT || Av1I2cClock (A/V Encoder DRH I²C Clock)
|-
| 24 || LATTE || NONE || Reserved
|-
| 25 || ALL || OUT || Av1I2cData (A/V Encoder DRH I²C Data)
|-
| 25 || LATTE || NONE || Reserved
|-
| 26 || ALL || OUT || MuteLamp
|-
| 26 || LATTE || NONE || Reserved
|-
| 27 || ALL || OUT || BluetoothMode
|-
| 27 || LATTE || NONE || Reserved
|-
| 28 || ALL || OUT || CcrhReset
|-
| 28 || LATTE || NONE || Reserved
|-
| 29 || ALL || OUT || WifiMode
|-
| 29 || LATTE || NONE || Reserved
|-
| 30 || ALL || OUT || Sdcc0s0Power (SD card power, driven low before boot0 attempts to read a signed boot1 image from the SD card)
|-
| 30 || LATTE || NONE || Reserved
|-
| 31 || ALL || I/O || ToucanSelect (devkit only)
|-
| 31 || LATTE || NONE || Reserved
|}
|}


== Register list ==
== Register list ==
{{reglist|Wood and Latte GPIOs (ALL)}}
{{reglist|Wood and Latte GPIOs (ALL)}}
{{rla|0x0d8000c0|32|HW_GPIOB_OUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d8000c0|32|HW_GPIOPPCOUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d8000c4|32|HW_GPIOB_DIR|GPIO Direction (Espresso access)}}
{{rla|0x0d8000c4|32|HW_GPIOPPCOE|GPIO Output Enable (Espresso access)}}
{{rla|0x0d8000c8|32|HW_GPIOB_IN|GPIO Inputs (Espresso access)}}
{{rla|0x0d8000c8|32|HW_GPIOPPCIN|GPIO Inputs (Espresso access)}}
{{rla|0x0d8000cc|32|HW_GPIOB_INTLVL|GPIO Interrupt Levels (Espresso access)}}
{{rla|0x0d8000cc|32|HW_GPIOPPCINTPOL|GPIO Interrupt Polarity (Espresso access)}}
{{rla|0x0d8000d0|32|HW_GPIOB_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d8000d0|32|HW_GPIOPPCINTSTS|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d8000d4|32|HW_GPIOB_INTMASK|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d8000d4|32|HW_GPIOPPCINTEN|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d8000d8|32|HW_GPIOB_STRAPS|GPIO Straps (Espresso access)}}
{{rla|0x0d8000d8|32|HW_GPIOPPCSTRAPS|GPIO Straps (Espresso access)}}
{{rla|0x0d8000dc|32|HW_GPIO_ENABLE|GPIO Enable (Starbuck only)}}
{{rla|0x0d8000dc|32|HW_GPIOIOPEN|GPIO Enable (Starbuck access)}}
{{rla|0x0d8000e0|32|HW_GPIO_OUT|GPIO Outputs (Starbuck only)}}
{{rla|0x0d8000e0|32|HW_GPIOIOPOUT|GPIO Outputs (Starbuck access)}}
{{rla|0x0d8000e4|32|HW_GPIO_DIR|GPIO Direction (Starbuck only)}}
{{rla|0x0d8000e4|32|HW_GPIOIOPOE|GPIO Output Enable (Starbuck access)}}
{{rla|0x0d8000e8|32|HW_GPIO_IN|GPIO Inputs (Starbuck only)}}
{{rla|0x0d8000e8|32|HW_GPIOIOPIN|GPIO Inputs (Starbuck access)}}
{{rla|0x0d8000ec|32|HW_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
{{rla|0x0d8000ec|32|HW_GPIOIOPINTPOL|GPIO Interrupt Polarity (Starbuck access)}}
{{rla|0x0d8000f0|32|HW_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
{{rla|0x0d8000f0|32|HW_GPIOIOPINTSTS|GPIO Interrupt Flags (Starbuck access)}}
{{rla|0x0d8000f4|32|HW_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
{{rla|0x0d8000f4|32|HW_GPIOIOPINTEN|GPIO Interrupt Masks (Starbuck access)}}
{{rla|0x0d8000f8|32|HW_GPIO_STRAPS|GPIO Straps (Starbuck only)}}
{{rla|0x0d8000f8|32|HW_GPIOIOPSTRAPS|GPIO Straps (Starbuck access)}}
{{rla|0x0d8000fc|32|HW_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
{{rla|0x0d8000fc|32|HW_GPIOIOPPPCOWNER|GPIO Owner Select (Starbuck access)}}
|}
|}




{{reglist|Latte GPIOs (LT)}}
{{reglist|Latte GPIOs (LATTE)}}
{{rla|0x0d800520|32|LT_GPIOB_OUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d800520|32|LT_GPIOPPCOUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d800524|32|LT_GPIOB_DIR|GPIO Direction (Espresso access)}}
{{rla|0x0d800524|32|LT_GPIOPPCOE|GPIO Output Enable (Espresso access)}}
{{rla|0x0d800528|32|LT_GPIOB_IN|GPIO Inputs (Espresso access)}}
{{rla|0x0d800528|32|LT_GPIOPPCIN|GPIO Inputs (Espresso access)}}
{{rla|0x0d80052c|32|LT_GPIOB_INTLVL|GPIO Interrupt Levels (Espresso access)}}
{{rla|0x0d80052c|32|LT_GPIOPPCINTPOL|GPIO Interrupt Polarity (Espresso access)}}
{{rla|0x0d800530|32|LT_GPIOB_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d800530|32|LT_GPIOPPCINTSTS|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d800534|32|LT_GPIOB_INTMASK|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d800534|32|LT_GPIOPPCINTEN|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d800538|32|LT_GPIOB_STRAPS|GPIO Straps (Espresso access)}}
{{rla|0x0d800538|32|LT_GPIOPPCSTRAPS|GPIO Straps (Espresso access)}}
{{rla|0x0d80053c|32|LT_GPIO_ENABLE|GPIO Enable (Starbuck only)}}
{{rla|0x0d80053c|32|LT_GPIOIOPEN|GPIO Enable (Starbuck access)}}
{{rla|0x0d800540|32|LT_GPIO_OUT|GPIO Outputs (Starbuck only)}}
{{rla|0x0d800540|32|LT_GPIOIOPOUT|GPIO Outputs (Starbuck access)}}
{{rla|0x0d800544|32|LT_GPIO_DIR|GPIO Direction (Starbuck only)}}
{{rla|0x0d800544|32|LT_GPIOIOPOE|GPIO Output Enable (Starbuck access)}}
{{rla|0x0d800548|32|LT_GPIO_IN|GPIO Inputs (Starbuck only)}}
{{rla|0x0d800548|32|LT_GPIOIOPIN|GPIO Inputs (Starbuck access)}}
{{rla|0x0d80054c|32|LT_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
{{rla|0x0d80054c|32|LT_GPIOIOPINTPOL|GPIO Interrupt Polarity (Starbuck access)}}
{{rla|0x0d800550|32|LT_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
{{rla|0x0d800550|32|LT_GPIOIOPINTSTS|GPIO Interrupt Flags (Starbuck access)}}
{{rla|0x0d800554|32|LT_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
{{rla|0x0d800554|32|LT_GPIOIOPINTEN|GPIO Interrupt Masks (Starbuck access)}}
{{rla|0x0d800558|32|LT_GPIO_STRAPS|GPIO Straps (Starbuck only)}}
{{rla|0x0d800558|32|LT_GPIOIOPSTRAPS|GPIO Straps (Starbuck access)}}
{{rla|0x0d80055c|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
{{rla|0x0d80055c|32|LT_GPIOIOPPPCOWNER|GPIO Owner Select (Starbuck access)}}
|}
|}


== Register descriptions ==
== Register descriptions ==
{{regsimple2|HW_GPIO_ENABLE|addr=0x0d8000dc|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOIOPEN|addr=0x0d8000dc|bits=32|split=24|access=R/W}}
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
----
----
{{regsimple2|HW_GPIO_OUT|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOIOPOUT|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
----
----
{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOIOPOE|addr=0x0d8000e4|bits=32|split=24|access=R/W}}
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
----
----
{{regsimple2|HW_GPIO_IN|addr=0x0d8000e8|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOIOPIN|addr=0x0d8000e8|bits=32|split=24|access=R}}
This register can be read to obtain the current input value of the GPIO pins.
This register can be read to obtain the current input value of the GPIO pins.
----
----
{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOIOPINTPOL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
----
----
{{regsimple2|HW_GPIO_INTFLAG|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}
{{regsimple2|HW_GPIOIOPINTSTS|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIO_INTLVL register, then the corresponding bit in HW_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in HW_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIOIOPINTPOL register, then the corresponding bit in HW_GPIOIOPINTSTS will be stuck at one until the pin state reverts or the value in HW_GPIOIOPINTPOL  is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
----
----
{{regsimple2|HW_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOIOPINTEN|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~HW_GPIO_OWNER.
Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|GPIIOP]] interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIOIOPINTSTS. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIOIOPINTEN & HW_GPIOIOPINTSTS & ~HW_GPIOIOPPPCOWNER.
----
----
{{regsimple2|HW_GPIO_STRAPS|addr=0x0d8000f8|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOIOPSTRAPS|addr=0x0d8000f8|bits=32|split=24|access=R}}
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.
----
----
{{regsimple2|HW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOIOPPPCOWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}
This register configures which pins can be controlled by the HW_GPIOB_* registers. A one bit configures the pin for control via the HW_GPIOB_* registers, which lets it be accessed by the Espresso. A zero bit restricts access to the HW_GPIO_* registers, which are Starbuck-only. The HW_GPIO_* registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOB_* registers if the corresponding bit is set in the HW_GPIO_OWNER register.
This register configures which pins can be controlled by the HW_GPIOPPC* registers. A one bit configures the pin for control via the HW_GPIOPPC* registers, which lets it be accessed by the Espresso. A zero bit restricts access to the HW_GPIOIOP* registers, which are Starbuck-only. The HW_GPIOIOP* registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOPPC* registers if the corresponding bit is set in the HW_GPIOIOPPPCOWNER register.
----
----
{{regsimple2|HW_GPIOB_OUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOPPCOUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_DIR|addr=0x0d8000c4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOPPCOE|addr=0x0d8000c4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_IN|addr=0x0d8000c8|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOPPCIN|addr=0x0d8000c8|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOB_INTLVL|addr=0x0d8000cc|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOPPCINTPOL|addr=0x0d8000cc|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}
{{regsimple2|HW_GPIOPPCINTSTS|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}
{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOPPCINTEN|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|HW_GPIOB_STRAPS|addr=0x0d8000d8|bits=32|split=24|access=R}}
{{regsimple2|HW_GPIOPPCSTRAPS|addr=0x0d8000d8|bits=32|split=24|access=R}}
These registers operate identically to their HW_GPIO_* counterparts above, but they only control the pins which have their respective HW_GPIO_OWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the [[Hardware/Latte_IRQ_Controller|GPIOB interrupt]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the HW_GPIOB_* registers are already masked with the HW_GPIO_OWNER register.
These registers operate identically to their HW_GPIOIOP* counterparts above, but they only control the pins which have their respective HW_GPIOIOPPPCOWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the [[Hardware/Latte_IRQ_Controller|GPIPPC]] interrupt (#10). The generation logic would be HW_GPIOPPCINTSTS & HW_GPIOPPCINTEN, with an implicit AND with HW_GPIOIOPPPCOWNER since the HW_GPIOPPC* registers are already masked with the HW_GPIOIOPPPCOWNER register.


When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO_* registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB_* registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB_* registers have to that data.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIOIOP* registers, and that bit is then set in the HW_GPIOIOPPPCOWNER  register, those settings will immediately be visible in the HW_GPIOB_* registers. There is only one set of data registers, and the HW_GPIOIOPPPCOWNER register just controls the access that the HW_GPIOPPC* registers have to that data.
----
----
{{regsimple2|LT_GPIOB_OUT|addr=0x0d800520|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOPPCOUT|addr=0x0d800520|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOB_DIR|addr=0x0d800524|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOPPCOE|addr=0x0d800524|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOB_IN|addr=0x0d800528|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOPPCIN|addr=0x0d800528|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOB_INTLVL|addr=0x0d80052c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOPPCINTPOL|addr=0x0d80052c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOB_INTFLAG|addr=0x0d800530|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIOPPCINTSTS|addr=0x0d800530|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIOB_INTMASK|addr=0x0d800534|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOPPCINTEN|addr=0x0d800534|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOB_STRAPS|addr=0x0d800538|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOPPCSTRAPS|addr=0x0d800538|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO_ENABLE|addr=0x0d80053c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOIOPEN|addr=0x0d80053c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO_OUT|addr=0x0d800540|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOIOPOUT|addr=0x0d800540|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO_DIR|addr=0x0d800544|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOIOPOE|addr=0x0d800544|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO_IN|addr=0x0d800548|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOIOPIN|addr=0x0d800548|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO_INTLVL|addr=0x0d80054c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOIOPINTPOL|addr=0x0d80054c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO_INTFLAG|addr=0x0d800550|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIOIOPINTSTS|addr=0x0d800550|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIO_INTMASK|addr=0x0d800554|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOIOPINTEN|addr=0x0d800554|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO_STRAPS|addr=0x0d800558|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOIOPSTRAPS|addr=0x0d800558|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO_OWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOIOPPPCOWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}
These registers work identically to those used for the first GPIO group.
These registers work identically to those used for the first GPIO group.



Latest revision as of 03:57, 30 May 2025

Latte GPIOs
Latte Registers
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d8000c0, 0x0d800520
Length0x80
Access size32 bits
Byte orderBig Endian
IRQs
EspressoNone
Latte10,11
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The Latte chipset includes two groups of general purpose I/O lines with interrupt capability: one common to Wood and Latte hardware (ALL) and another exclusively available to Latte (LATTE). Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.

Pins

Bit Group Direction Description
0 ALL IN RtcSysInt
0 LATTE OUT FanSpeed
1 ALL OUT DwifiMode
1 LATTE IN SmcScl
2 ALL OUT FanPower
2 LATTE IN SmcSda
3 ALL OUT DcdcPowerControl (active high) or CcrhIo3 (Evaluation or Cortado boards only)
3 LATTE OUT DcdcPowerControl2 (active high)
4 ALL OUT NC (not connected) or DISpinUp (Cortado boards only)
4 LATTE IN AvInt (A/V encoder interrupt from Espresso)
5 ALL OUT Esp10Workaround or SlotLED (Cortado boards only)
5 LATTE OUT CcrhIo12 or CCRHFWCtrl (Cortado boards only)
6 ALL OUT DRCPWRREQ
6 LATTE OUT AvReset (A/V encoder reset from Espresso)
7 ALL IN JIG
7 LATTE NONE Reserved
8 ALL OUT PadPd (GamePad power state)
8 LATTE NONE Reserved
9 ALL I/O ToucanSelect (devkit only)
9 LATTE NONE Reserved
10 ALL OUT EepromCs (EEPROM chip select)
10 LATTE NONE Reserved
11 ALL OUT EepromSk (EEPROM clock)
11 LATTE NONE Reserved
12 ALL OUT EepromDo (data to EEPROM)
12 LATTE NONE Reserved
13 ALL IN EepromDi (data from EEPROM)
13 LATTE NONE Reserved
14 ALL OUT Av0I2cClock (A/V Encoder 4IN1 I²C Clock)
14 LATTE NONE Reserved
15 ALL OUT Av0I2cData (A/V Encoder 4IN1 I²C Data)
15 LATTE NONE Reserved
16 ALL OUT NdevLed0 (devkit only, debug testpoint TP50)
16 LATTE NONE Reserved
17 ALL OUT NdevLed1 (devkit only, debug testpoint TP51)
17 LATTE NONE Reserved
18 ALL OUT NdevLed2 (devkit only, debug testpoint TP52)
18 LATTE NONE Reserved
19 ALL OUT NdevLed3 (devkit only, debug testpoint TP53)
19 LATTE NONE Reserved
20 ALL OUT NdevLed4 (devkit only, debug testpoint TP55)
20 LATTE NONE Reserved
21 ALL OUT NdevLed5 (devkit only, debug testpoint TP54)
21 LATTE NONE Reserved
22 ALL OUT NdevLed6 (devkit only, debug testpoint TP48)
22 LATTE NONE Reserved
23 ALL OUT NdevLed7 (devkit only, debug testpoint TP49)
23 LATTE NONE Reserved
24 ALL OUT Av1I2cClock (A/V Encoder DRH I²C Clock)
24 LATTE NONE Reserved
25 ALL OUT Av1I2cData (A/V Encoder DRH I²C Data)
25 LATTE NONE Reserved
26 ALL OUT MuteLamp
26 LATTE NONE Reserved
27 ALL OUT BluetoothMode
27 LATTE NONE Reserved
28 ALL OUT CcrhReset
28 LATTE NONE Reserved
29 ALL OUT WifiMode
29 LATTE NONE Reserved
30 ALL OUT Sdcc0s0Power (SD card power, driven low before boot0 attempts to read a signed boot1 image from the SD card)
30 LATTE NONE Reserved
31 ALL I/O ToucanSelect (devkit only)
31 LATTE NONE Reserved

Register list

Wood and Latte GPIOs (ALL)
Address Bits Name Description
0x0d8000c0 32 HW_GPIOPPCOUT GPIO Outputs (Espresso access)
0x0d8000c4 32 HW_GPIOPPCOE GPIO Output Enable (Espresso access)
0x0d8000c8 32 HW_GPIOPPCIN GPIO Inputs (Espresso access)
0x0d8000cc 32 HW_GPIOPPCINTPOL GPIO Interrupt Polarity (Espresso access)
0x0d8000d0 32 HW_GPIOPPCINTSTS GPIO Interrupt Flags (Espresso access)
0x0d8000d4 32 HW_GPIOPPCINTEN GPIO Interrupt Masks (Espresso access)
0x0d8000d8 32 HW_GPIOPPCSTRAPS GPIO Straps (Espresso access)
0x0d8000dc 32 HW_GPIOIOPEN GPIO Enable (Starbuck access)
0x0d8000e0 32 HW_GPIOIOPOUT GPIO Outputs (Starbuck access)
0x0d8000e4 32 HW_GPIOIOPOE GPIO Output Enable (Starbuck access)
0x0d8000e8 32 HW_GPIOIOPIN GPIO Inputs (Starbuck access)
0x0d8000ec 32 HW_GPIOIOPINTPOL GPIO Interrupt Polarity (Starbuck access)
0x0d8000f0 32 HW_GPIOIOPINTSTS GPIO Interrupt Flags (Starbuck access)
0x0d8000f4 32 HW_GPIOIOPINTEN GPIO Interrupt Masks (Starbuck access)
0x0d8000f8 32 HW_GPIOIOPSTRAPS GPIO Straps (Starbuck access)
0x0d8000fc 32 HW_GPIOIOPPPCOWNER GPIO Owner Select (Starbuck access)


Latte GPIOs (LATTE)
Address Bits Name Description
0x0d800520 32 LT_GPIOPPCOUT GPIO Outputs (Espresso access)
0x0d800524 32 LT_GPIOPPCOE GPIO Output Enable (Espresso access)
0x0d800528 32 LT_GPIOPPCIN GPIO Inputs (Espresso access)
0x0d80052c 32 LT_GPIOPPCINTPOL GPIO Interrupt Polarity (Espresso access)
0x0d800530 32 LT_GPIOPPCINTSTS GPIO Interrupt Flags (Espresso access)
0x0d800534 32 LT_GPIOPPCINTEN GPIO Interrupt Masks (Espresso access)
0x0d800538 32 LT_GPIOPPCSTRAPS GPIO Straps (Espresso access)
0x0d80053c 32 LT_GPIOIOPEN GPIO Enable (Starbuck access)
0x0d800540 32 LT_GPIOIOPOUT GPIO Outputs (Starbuck access)
0x0d800544 32 LT_GPIOIOPOE GPIO Output Enable (Starbuck access)
0x0d800548 32 LT_GPIOIOPIN GPIO Inputs (Starbuck access)
0x0d80054c 32 LT_GPIOIOPINTPOL GPIO Interrupt Polarity (Starbuck access)
0x0d800550 32 LT_GPIOIOPINTSTS GPIO Interrupt Flags (Starbuck access)
0x0d800554 32 LT_GPIOIOPINTEN GPIO Interrupt Masks (Starbuck access)
0x0d800558 32 LT_GPIOIOPSTRAPS GPIO Straps (Starbuck access)
0x0d80055c 32 LT_GPIOIOPPPCOWNER GPIO Owner Select (Starbuck access)

Register descriptions

HW_GPIOIOPEN (0x0d8000dc)
  3124 230
Access U R/W

The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.


HW_GPIOIOPOUT (0x0d8000e0)
  3124 230
Access U R/W

This register contains the output value for all pins. These only take effect if the pin is configured as an output.


HW_GPIOIOPOE (0x0d8000e4)
  3124 230
Access U R/W

A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.


HW_GPIOIOPIN (0x0d8000e8)
  3124 230
Access U R

This register can be read to obtain the current input value of the GPIO pins.


HW_GPIOIOPINTPOL (0x0d8000ec)
  3124 230
Access U R/W

Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.


HW_GPIOIOPINTSTS (0x0d8000f0)
  3124 230
Access U R/Z

Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIOIOPINTPOL register, then the corresponding bit in HW_GPIOIOPINTSTS will be stuck at one until the pin state reverts or the value in HW_GPIOIOPINTPOL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.


HW_GPIOIOPINTEN (0x0d8000f4)
  3124 230
Access U R/W

Only the bits set in this register propagate their interrupts to the master GPIIOP interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIOIOPINTSTS. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIOIOPINTEN & HW_GPIOIOPINTSTS & ~HW_GPIOIOPPPCOWNER.


HW_GPIOIOPSTRAPS (0x0d8000f8)
  3124 230
Access U R

This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.


HW_GPIOIOPPPCOWNER (0x0d8000fc)
  3124 230
Access U R/W

This register configures which pins can be controlled by the HW_GPIOPPC* registers. A one bit configures the pin for control via the HW_GPIOPPC* registers, which lets it be accessed by the Espresso. A zero bit restricts access to the HW_GPIOIOP* registers, which are Starbuck-only. The HW_GPIOIOP* registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOPPC* registers if the corresponding bit is set in the HW_GPIOIOPPPCOWNER register.


HW_GPIOPPCOUT (0x0d8000c0)
  3124 230
Access U R/W

HW_GPIOPPCOE (0x0d8000c4)
  3124 230
Access U R/W

HW_GPIOPPCIN (0x0d8000c8)
  3124 230
Access U R

HW_GPIOPPCINTPOL (0x0d8000cc)
  3124 230
Access U R/W

HW_GPIOPPCINTSTS (0x0d8000d0)
  3124 230
Access U R/Z

HW_GPIOPPCINTEN (0x0d8000d4)
  3124 230
Access U R/W

HW_GPIOPPCSTRAPS (0x0d8000d8)
  3124 230
Access U R

These registers operate identically to their HW_GPIOIOP* counterparts above, but they only control the pins which have their respective HW_GPIOIOPPPCOWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the GPIPPC interrupt (#10). The generation logic would be HW_GPIOPPCINTSTS & HW_GPIOPPCINTEN, with an implicit AND with HW_GPIOIOPPPCOWNER since the HW_GPIOPPC* registers are already masked with the HW_GPIOIOPPPCOWNER register.

When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIOIOP* registers, and that bit is then set in the HW_GPIOIOPPPCOWNER register, those settings will immediately be visible in the HW_GPIOB_* registers. There is only one set of data registers, and the HW_GPIOIOPPPCOWNER register just controls the access that the HW_GPIOPPC* registers have to that data.


LT_GPIOPPCOUT (0x0d800520)
  3124 230
Access U R/W

LT_GPIOPPCOE (0x0d800524)
  3124 230
Access U R/W

LT_GPIOPPCIN (0x0d800528)
  3124 230
Access U R

LT_GPIOPPCINTPOL (0x0d80052c)
  3124 230
Access U R/W

LT_GPIOPPCINTSTS (0x0d800530)
  3124 230
Access U R/Z

LT_GPIOPPCINTEN (0x0d800534)
  3124 230
Access U R/W

LT_GPIOPPCSTRAPS (0x0d800538)
  3124 230
Access U R

LT_GPIOIOPEN (0x0d80053c)
  3124 230
Access U R/W

LT_GPIOIOPOUT (0x0d800540)
  3124 230
Access U R/W

LT_GPIOIOPOE (0x0d800544)
  3124 230
Access U R/W

LT_GPIOIOPIN (0x0d800548)
  3124 230
Access U R

LT_GPIOIOPINTPOL (0x0d80054c)
  3124 230
Access U R/W

LT_GPIOIOPINTSTS (0x0d800550)
  3124 230
Access U R/Z

LT_GPIOIOPINTEN (0x0d800554)
  3124 230
Access U R/W

LT_GPIOIOPSTRAPS (0x0d800558)
  3124 230
Access U R

LT_GPIOIOPPPCOWNER (0x0d80055c)
  3124 230
Access U R/W

These registers work identically to those used for the first GPIO group.

Debug pins

The following debug pins are located on the bottom of the mainboard. The numbers represent DEBUG0 - DEBUG7 from the pin connection list above.