Hardware/Latte GPIOs
| Latte GPIOs | |
| Latte Registers | |
| Access | |
|---|---|
| Espresso | Partial |
| Starbuck | Full |
| Registers | |
| Base | 0x0d8000c0, 0x0d800520 |
| Length | 0x80 |
| Access size | 32 bits |
| Byte order | Big Endian |
| IRQs | |
| Espresso | None |
| Latte | 10,11 |
The Latte chipset includes two groups of general purpose I/O lines with interrupt capability: one common to Wood and Latte hardware (ALL) and another exclusively available to Latte (LATTE). Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.
Pins
| Bit | Group | Direction | Description |
|---|---|---|---|
| 0 | ALL | IN | RTCSysInt (power button input) |
| 0 | ALL | OUT | ToucanSelect (Toucan select, devkit only) |
| 0 | LATTE | OUT | FanSpeed |
| 1 | ALL | OUT | DWiFiMode |
| 1 | LATTE | IN | SMCI2CClock |
| 2 | ALL | OUT | FanPower |
| 2 | LATTE | IN | SMCI2CData |
| 3 | ALL | OUT | DCDCPwrCnt (DC/DC converter power, active high) |
| 3 | ALL | OUT | CCRIO3 (DRH reset related, Cortado only, equiv to CCRHReset?) |
| 3 | LATTE | OUT | DCDCPwrCnt2 (DC/DC converter power, active high) |
| 4 | ALL | OUT | DISpinUp (devkit only) |
| 4 | LATTE | IN | AVInterrupt (A/V encoder interrupt from Espresso) |
| 5 | ALL | OUT | ESP10WorkAround |
| 5 | ALL | OUT | SlotLED (devkit only) |
| 5 | LATTE | OUT | CCRHFWCtrl (devkit only) |
| 6 | ALL | UNK | Unknown |
| 6 | LATTE | OUT | AVReset (A/V encoder reset from Espresso) |
| 7 | ALL | UNK | Unknown |
| 8 | ALL | OUT | PADPD (GamePad power state) |
| 9 | ALL | I/O | NDEV_LED (devkit only) |
| 10 | ALL | OUT | EEPROM_CS (SEEPROM chip select) |
| 11 | ALL | OUT | EEPROM_SK (SEEPROM clock) |
| 12 | ALL | OUT | EEPROM_DO (data to SEEPROM) |
| 13 | ALL | IN | EEPROM_DI (data from SEEPROM) |
| 14 | ALL | OUT | AV0I2CClock (A/V Encoder #0 I²C Clock) |
| 15 | ALL | OUT | AV0I2CData (A/V Encoder #0 I²C Data) |
| 16 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP50) |
| 17 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP51) |
| 18 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP52) |
| 19 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP53) |
| 20 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP55) |
| 21 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP54) |
| 22 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP48) |
| 23 | ALL | I/O | NDEV_LED (devkit only, debug testpoint TP49) |
| 24 | ALL | OUT | AV1I2CClock (A/V Encoder #1 I²C Clock) |
| 25 | ALL | OUT | AV1I2CData (A/V Encoder #1 I²C Data) |
| 26 | ALL | OUT | MuteLamp |
| 27 | ALL | OUT | BlueToothMode |
| 28 | ALL | OUT | CCRHReset |
| 29 | ALL | OUT | WiFiMode |
| 30 | ALL | OUT | SDC0S0Power (SD card power, driven low before boot0 attempts to read a signed boot1 image from the SD card) |
| 31 | ALL | I/O | NDEV_LED (devkit only) |
Register list
| Wood and Latte GPIOs (ALL) | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d8000c0 | 32 | HW_GPIOPPCOUT | GPIO Outputs (Espresso access) |
| 0x0d8000c4 | 32 | HW_GPIOPPCDIR | GPIO Direction (Espresso access) |
| 0x0d8000c8 | 32 | HW_GPIOPPCIN | GPIO Inputs (Espresso access) |
| 0x0d8000cc | 32 | HW_GPIOPPCINTLVL | GPIO Interrupt Levels (Espresso access) |
| 0x0d8000d0 | 32 | HW_GPIOPPCINTSTS | GPIO Interrupt Flags (Espresso access) |
| 0x0d8000d4 | 32 | HW_GPIOPPCINTEN | GPIO Interrupt Masks (Espresso access) |
| 0x0d8000d8 | 32 | HW_GPIOPPCSTRAPS | GPIO Straps (Espresso access) |
| 0x0d8000dc | 32 | HW_GPIOIOPEN | GPIO Enable (Starbuck access) |
| 0x0d8000e0 | 32 | HW_GPIOIOPOUT | GPIO Outputs (Starbuck access) |
| 0x0d8000e4 | 32 | HW_GPIOIOPDIR | GPIO Direction (Starbuck access) |
| 0x0d8000e8 | 32 | HW_GPIOIOPIN | GPIO Inputs (Starbuck access) |
| 0x0d8000ec | 32 | HW_GPIOIOPINTLVL | GPIO Interrupt Levels (Starbuck access) |
| 0x0d8000f0 | 32 | HW_GPIOIOPINTSTS | GPIO Interrupt Flags (Starbuck access) |
| 0x0d8000f4 | 32 | HW_GPIOIOPINTEN | GPIO Interrupt Masks (Starbuck access) |
| 0x0d8000f8 | 32 | HW_GPIOIOPSTRAPS | GPIO Straps (Starbuck access) |
| 0x0d8000fc | 32 | HW_GPIOIOPPPCOWNER | GPIO Owner Select (Starbuck access) |
| Latte GPIOs (LATTE) | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800520 | 32 | LT_GPIOPPCOUT | GPIO Outputs (Espresso access) |
| 0x0d800524 | 32 | LT_GPIOPPCDIR | GPIO Direction (Espresso access) |
| 0x0d800528 | 32 | LT_GPIOPPCIN | GPIO Inputs (Espresso access) |
| 0x0d80052c | 32 | LT_GPIOPPCINTLVL | GPIO Interrupt Levels (Espresso access) |
| 0x0d800530 | 32 | LT_GPIOPPCINTSTS | GPIO Interrupt Flags (Espresso access) |
| 0x0d800534 | 32 | LT_GPIOPPCINTEN | GPIO Interrupt Masks (Espresso access) |
| 0x0d800538 | 32 | LT_GPIOPPCSTRAPS | GPIO Straps (Espresso access) |
| 0x0d80053c | 32 | LT_GPIOIOPEN | GPIO Enable (Starbuck access) |
| 0x0d800540 | 32 | LT_GPIOIOPOUT | GPIO Outputs (Starbuck access) |
| 0x0d800544 | 32 | LT_GPIOIOPDIR | GPIO Direction (Starbuck access) |
| 0x0d800548 | 32 | LT_GPIOIOPIN | GPIO Inputs (Starbuck access) |
| 0x0d80054c | 32 | LT_GPIOIOPINTLVL | GPIO Interrupt Levels (Starbuck access) |
| 0x0d800550 | 32 | LT_GPIOIOPINTSTS | GPIO Interrupt Flags (Starbuck access) |
| 0x0d800554 | 32 | LT_GPIOIOPINTEN | GPIO Interrupt Masks (Starbuck access) |
| 0x0d800558 | 32 | LT_GPIOIOPSTRAPS | GPIO Straps (Starbuck access) |
| 0x0d80055c | 32 | LT_GPIOIOPPPCOWNER | GPIO Owner Select (Starbuck access) |
Register descriptions
| HW_GPIOIOPEN (0x0d8000dc) | ||
| 3124 | 230 | |
| Access | U | R/W |
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
| HW_GPIOIOPOUT (0x0d8000e0) | ||
| 3124 | 230 | |
| Access | U | R/W |
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
| HW_GPIOIOPDIR (0x0d8000e4) | ||
| 3124 | 230 | |
| Access | U | R/W |
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
| HW_GPIOIOPIN (0x0d8000e8) | ||
| 3124 | 230 | |
| Access | U | R |
This register can be read to obtain the current input value of the GPIO pins.
| HW_GPIOIOPINTLVL (0x0d8000ec) | ||
| 3124 | 230 | |
| Access | U | R/W |
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
| HW_GPIOIOPINTSTS (0x0d8000f0) | ||
| 3124 | 230 | |
| Access | U | R/Z |
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIOIOPINTLVL register, then the corresponding bit in HW_GPIOIOPINTSTS will be stuck at one until the pin state reverts or the value in HW_GPIOIOPINTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
| HW_GPIOIOPINTEN (0x0d8000f4) | ||
| 3124 | 230 | |
| Access | U | R/W |
Only the bits set in this register propagate their interrupts to the master GPIIOP interrupt (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIOIOPINTSTS. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIOIOPINTEN & HW_GPIOIOPINTSTS & ~HW_GPIOIOPPPCOWNER.
| HW_GPIOIOPSTRAPS (0x0d8000f8) | ||
| 3124 | 230 | |
| Access | U | R |
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.
| HW_GPIOIOPPPCOWNER (0x0d8000fc) | ||
| 3124 | 230 | |
| Access | U | R/W |
This register configures which pins can be controlled by the HW_GPIOPPC* registers. A one bit configures the pin for control via the HW_GPIOPPC* registers, which lets it be accessed by the Espresso. A zero bit restricts access to the HW_GPIOIOP* registers, which are Starbuck-only. The HW_GPIOIOP* registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOPPC* registers if the corresponding bit is set in the HW_GPIOIOPPPCOWNER register.
| HW_GPIOPPCOUT (0x0d8000c0) | ||
| 3124 | 230 | |
| Access | U | R/W |
| HW_GPIOPPCDIR (0x0d8000c4) | ||
| 3124 | 230 | |
| Access | U | R/W |
| HW_GPIOPPCIN (0x0d8000c8) | ||
| 3124 | 230 | |
| Access | U | R |
| HW_GPIOPPCINTLVL (0x0d8000cc) | ||
| 3124 | 230 | |
| Access | U | R/W |
| HW_GPIOPPCINTSTS (0x0d8000d0) | ||
| 3124 | 230 | |
| Access | U | R/Z |
| HW_GPIOPPCINTEN (0x0d8000d4) | ||
| 3124 | 230 | |
| Access | U | R/W |
| HW_GPIOPPCSTRAPS (0x0d8000d8) | ||
| 3124 | 230 | |
| Access | U | R |
These registers operate identically to their HW_GPIOIOP* counterparts above, but they only control the pins which have their respective HW_GPIOIOPPPCOWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the GPIPPC interrupt (#10). The generation logic would be HW_GPIOPPCINTSTS & HW_GPIOPPCINTEN, with an implicit AND with HW_GPIOIOPPPCOWNER since the HW_GPIOPPC* registers are already masked with the HW_GPIOIOPPPCOWNER register.
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIOIOP* registers, and that bit is then set in the HW_GPIOIOPPPCOWNER register, those settings will immediately be visible in the HW_GPIOB_* registers. There is only one set of data registers, and the HW_GPIOIOPPPCOWNER register just controls the access that the HW_GPIOPPC* registers have to that data.
| LT_GPIOPPCOUT (0x0d800520) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOPPCDIR (0x0d800524) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOPPCIN (0x0d800528) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIOPPCINTLVL (0x0d80052c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOPPCINTSTS (0x0d800530) | ||
| 3124 | 230 | |
| Access | U | R/Z |
| LT_GPIOPPCINTEN (0x0d800534) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOPPCSTRAPS (0x0d800538) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIOIOPEN (0x0d80053c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOIOPOUT (0x0d800540) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOIOPDIR (0x0d800544) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOIOPIN (0x0d800548) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIOIOPINTLVL (0x0d80054c) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOIOPINTSTS (0x0d800550) | ||
| 3124 | 230 | |
| Access | U | R/Z |
| LT_GPIOIOPINTEN (0x0d800554) | ||
| 3124 | 230 | |
| Access | U | R/W |
| LT_GPIOIOPSTRAPS (0x0d800558) | ||
| 3124 | 230 | |
| Access | U | R |
| LT_GPIOIOPPPCOWNER (0x0d80055c) | ||
| 3124 | 230 | |
| Access | U | R/W |
These registers work identically to those used for the first GPIO group.
Debug pins
The following debug pins are located on the bottom of the mainboard. The numbers represent DEBUG0 - DEBUG7 from the pin connection list above.
