Difference between revisions of "Hardware/Latte IRQs"
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Marionumber1 (talk | contribs) (Start Latte IRQ controller page, add several registers) |
Marionumber1 (talk | contribs) m (→Register List: Use Processor Interface reg naming style) |
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===Global ARM block=== | ===Global ARM block=== | ||
{{reglist|Global ARM block}} | {{reglist|Global ARM block}} | ||
| − | {{rla|0x0d800030|32| | + | {{rla|0x0d800030|32|LT_INTSR_PPC|Triggered IRQs for the PPC}} |
| − | {{rla|0x0d800034|32| | + | {{rla|0x0d800034|32|LT_INTMR_PPC|Allowed IRQs for the PPC}} |
| − | {{rla|0x0d800038|32| | + | {{rla|0x0d800038|32|LT_INTSR_ARM|Triggered IRQs for the ARM}} |
| − | {{rla|0x0d80003c|32| | + | {{rla|0x0d80003c|32|LT_INTMR_ARM|Allowed IRQs for the ARM}} |
|} | |} | ||
===SMP block=== | ===SMP block=== | ||
{{reglist|SMP block - PPC core 0}} | {{reglist|SMP block - PPC core 0}} | ||
| − | {{rla|0x0d800440|32| | + | {{rla|0x0d800440|32|LT_INTSR_AHBALL_PPC0|Triggered AHB (all) IRQs for PPC core 0}} |
| − | {{rla|0x0d800444|32| | + | {{rla|0x0d800444|32|LT_INTSR_AHBLT_PPC0|Triggered AHB (Latte) IRQs for PPC core 0}} |
| − | {{rla|0x0d800448|32| | + | {{rla|0x0d800448|32|LT_INTMR_AHBALL_PPC0|Allowed AHB (all) IRQs for PPC core 0}} |
| − | {{rla|0x0d80044c|32| | + | {{rla|0x0d80044c|32|LT_INTMR_AHBLT_PPC0|Allowed AHB (Latte) IRQs for PPC core 0}} |
|} | |} | ||
{{reglist|SMP block - PPC core 1}} | {{reglist|SMP block - PPC core 1}} | ||
| − | {{rla|0x0d800450|32| | + | {{rla|0x0d800450|32|LT_INTSR_AHBALL_PPC1|Triggered AHB (all) IRQs for PPC core 1}} |
| − | {{rla|0x0d800454|32| | + | {{rla|0x0d800454|32|LT_INTSR_AHBLT_PPC1|Triggered AHB (Latte) IRQs for PPC core 1}} |
| − | {{rla|0x0d800458|32| | + | {{rla|0x0d800458|32|LT_INTMR_AHBALL_PPC1|Allowed AHB (all) IRQs for PPC core 1}} |
| − | {{rla|0x0d80045c|32| | + | {{rla|0x0d80045c|32|LT_INTMR_AHBLT_PPC1|Allowed AHB (Latte) IRQs for PPC core 1}} |
|} | |} | ||
{{reglist|SMP block - PPC core 2}} | {{reglist|SMP block - PPC core 2}} | ||
| − | {{rla|0x0d800460|32| | + | {{rla|0x0d800460|32|LT_INTSR_AHBALL_PPC2|Triggered AHB (all) IRQs for PPC core 2}} |
| − | {{rla|0x0d800464|32| | + | {{rla|0x0d800464|32|LT_INTSR_AHBLT_PPC2|Triggered AHB (Latte) IRQs for PPC core 2}} |
| − | {{rla|0x0d800468|32| | + | {{rla|0x0d800468|32|LT_INTMR_AHBALL_PPC2|Allowed AHB (all) IRQs for PPC core 2}} |
| − | {{rla|0x0d80046c|32| | + | {{rla|0x0d80046c|32|LT_INTMR_AHBLT_PPC2|Allowed AHB (Latte) IRQs for PPC core 2}} |
|} | |} | ||
Revision as of 19:59, 24 October 2015
| Latte IRQs | |
| Access | |
|---|---|
| Espresso | Partial |
| Starbuck | Full |
| Registers | |
| Base | 0x0d800030, 0x0d800440 |
| Length | 0x10, 0x48 |
| Access size | 32 bits |
| Byte order | Big Endian |
IRQ Sources
Register List
The Latte IRQ controller has two different register blocks: a global ARM block mapped at the same address as on the Wii, and a new SMP block for each PPC core to use.
Global ARM block
| Global ARM block | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800030 | 32 | LT_INTSR_PPC | Triggered IRQs for the PPC |
| 0x0d800034 | 32 | LT_INTMR_PPC | Allowed IRQs for the PPC |
| 0x0d800038 | 32 | LT_INTSR_ARM | Triggered IRQs for the ARM |
| 0x0d80003c | 32 | LT_INTMR_ARM | Allowed IRQs for the ARM |
SMP block
| SMP block - PPC core 0 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800440 | 32 | LT_INTSR_AHBALL_PPC0 | Triggered AHB (all) IRQs for PPC core 0 |
| 0x0d800444 | 32 | LT_INTSR_AHBLT_PPC0 | Triggered AHB (Latte) IRQs for PPC core 0 |
| 0x0d800448 | 32 | LT_INTMR_AHBALL_PPC0 | Allowed AHB (all) IRQs for PPC core 0 |
| 0x0d80044c | 32 | LT_INTMR_AHBLT_PPC0 | Allowed AHB (Latte) IRQs for PPC core 0 |
| SMP block - PPC core 1 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800450 | 32 | LT_INTSR_AHBALL_PPC1 | Triggered AHB (all) IRQs for PPC core 1 |
| 0x0d800454 | 32 | LT_INTSR_AHBLT_PPC1 | Triggered AHB (Latte) IRQs for PPC core 1 |
| 0x0d800458 | 32 | LT_INTMR_AHBALL_PPC1 | Allowed AHB (all) IRQs for PPC core 1 |
| 0x0d80045c | 32 | LT_INTMR_AHBLT_PPC1 | Allowed AHB (Latte) IRQs for PPC core 1 |
| SMP block - PPC core 2 | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d800460 | 32 | LT_INTSR_AHBALL_PPC2 | Triggered AHB (all) IRQs for PPC core 2 |
| 0x0d800464 | 32 | LT_INTSR_AHBLT_PPC2 | Triggered AHB (Latte) IRQs for PPC core 2 |
| 0x0d800468 | 32 | LT_INTMR_AHBALL_PPC2 | Allowed AHB (all) IRQs for PPC core 2 |
| 0x0d80046c | 32 | LT_INTMR_AHBLT_PPC2 | Allowed AHB (Latte) IRQs for PPC core 2 |