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Hardware/Latte registers (view source)

Revision as of 23:00, 28 October 2015

4,171 bytes added ,  23:00, 28 October 2015
More information on the Latte registers
Line 18: Line 18:  
{{rld|0x0d800010|32|LT_TIMER|[[Hardware/Starbuck Timer|Starbuck Timer]]|drs=2}}
 
{{rld|0x0d800010|32|LT_TIMER|[[Hardware/Starbuck Timer|Starbuck Timer]]|drs=2}}
 
{{rld|0x0d800014|32|LT_ALARM}}
 
{{rld|0x0d800014|32|LT_ALARM}}
−
{{rld|0x0d800030|32|LT_PPCIRQFLAG|[[Hardware/Latte_IRQ_Controller|Latte_IRQ_Controller]]|drs=4}}
+
{{rld|0x0d800030|32|LT_INTSR_PPC|[[Hardware/Latte_IRQ_Controller|Latte_IRQ_Controller]]|drs=4}}
−
{{rld|0x0d800034|32|LT_PPCIRQMASK}}
+
{{rld|0x0d800034|32|LT_INTMR_PPC}}
−
{{rld|0x0d800038|32|LT_ARMIRQFLAG}}
+
{{rld|0x0d800038|32|LT_INTSR_ARM}}
−
{{rld|0x0d80003c|32|LT_ARMIRQMASK}}
+
{{rld|0x0d80003c|32|LT_INTMR_ARM}}
 +
{{rld|0x0d800040|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80004c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800050|32|LT_SYSPROTDRV_UNK1|System protection driver|drs=4}}
 +
{{rld|0x0d800054|32|LT_SYSPROTDRV_UNK2}}
 +
{{rld|0x0d800058|32|LT_SYSPROTDRV_UNK3}}
 +
{{rld|0x0d80005c|32|LT_SYSPROTDRV_UNK4}}
 
{{rld|0x0d800060|32|LT_MEMIRR|Memory control{{check}}}}
 
{{rld|0x0d800060|32|LT_MEMIRR|Memory control{{check}}}}
 
{{rld|0x0d800064|32|LT_AHBPROT|Access control for the PPC to access devices on the AHB}}
 
{{rld|0x0d800064|32|LT_AHBPROT|Access control for the PPC to access devices on the AHB}}
−
{{rla|0x0d800070|32|LT_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
+
{{rld|0x0d800068|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80006c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800070|32|LT_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
 +
{{rld|0x0d800074|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800088|32|UNKNOWN|DDR?}}
 
{{rld|0x0d8000c0|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
 
{{rld|0x0d8000c0|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
 
{{rld|0x0d8000c4|32|LT_GPIOB_DIR}}
 
{{rld|0x0d8000c4|32|LT_GPIOB_DIR}}
Line 41: Line 51:  
{{rld|0x0d8000f8|32|LT_GPIO_INMIR}}
 
{{rld|0x0d8000f8|32|LT_GPIO_INMIR}}
 
{{rld|0x0d8000fc|32|LT_GPIO_OWNER}}
 
{{rld|0x0d8000fc|32|LT_GPIO_OWNER}}
−
{{rla|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
+
{{rld|0x0d800100|32|LT_AHB_UNK1|AHB specific registers|drs=13}}
 +
{{rld|0x0d800104|32|LT_AHB_UNK2}}
 +
{{rld|0x0d800108|32|LT_AHB_UNK3}}
 +
{{rld|0x0d80010c|32|LT_AHB_UNK4}}
 +
{{rld|0x0d800110|32|LT_AHB_UNK5}}
 +
{{rld|0x0d800114|32|LT_AHB_UNK6}}
 +
{{rld|0x0d800118|32|LT_AHB_UNK7}}
 +
{{rld|0x0d80011c|32|LT_AHB_UNK8}}
 +
{{rld|0x0d800120|32|LT_AHB_UNK9}}
 +
{{rld|0x0d800124|32|LT_AHB_UNK10}}
 +
{{rld|0x0d800130|32|LT_AHB_UNK11}}
 +
{{rld|0x0d800134|32|LT_AHB_UNK12}}
 +
{{rld|0x0d800138|32|LT_AHB_UNK13}}
 +
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
 +
{{rld|0x0d800184|32|LT_UNKFLAGS|Unknown flags}}
 +
{{rld|0x0d800188|32|UNKNOWN|Unknown}}
 
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
 
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
−
{{rla|0x0d800190|32|LT_CLOCKS|Clock stuff?}}
+
{{rld|0x0d800190|32|LT_CLOCKS|Clock stuff?}}
−
{{rla|0x0d800194|32|LT_RESETS|System resets / power{{check}}}}
+
{{rld|0x0d800194|32|LT_RESETS|System resets / power{{check}}}}
 
{{rld|0x0d800198|32|LT_IFPOWER|Interfaces' power state (set by IOS-BSP)}}
 
{{rld|0x0d800198|32|LT_IFPOWER|Interfaces' power state (set by IOS-BSP)}}
 +
{{rld|0x0d8001a8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8001c8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8001cc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8001d0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8001dc|32|LT_SSPOWER|Subsystems' power state (set by IOS-BSP)}}
 
{{rld|0x0d8001dc|32|LT_SSPOWER|Subsystems' power state (set by IOS-BSP)}}
 +
{{rld|0x0d8001e0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8001e4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8001e8|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001f0|32|LT_OTPDATA}}
 
{{rld|0x0d8001f0|32|LT_OTPDATA}}
 +
{{rld|0x0d800204|32|UNKNOWN|Unknown}}
 
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
 
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
 +
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800258|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800400|32|LT_IPC_PPC0_PPCMSG|[[Hardware/IPC|IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800400|32|LT_IPC_PPC0_PPCMSG|[[Hardware/IPC|IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800404|32|LT_IPC_PPC0_PPCCTRL}}
 
{{rld|0x0d800404|32|LT_IPC_PPC0_PPCCTRL}}
Line 62: Line 99:  
{{rld|0x0d800428|32|LT_IPC_PPC2_ARMMSG}}
 
{{rld|0x0d800428|32|LT_IPC_PPC2_ARMMSG}}
 
{{rld|0x0d80042c|32|LT_IPC_PPC2_ARMCTRL}}
 
{{rld|0x0d80042c|32|LT_IPC_PPC2_ARMCTRL}}
 +
{{rld|0x0d800440|32|LT_INTSR_AHBALL_PPC0|[[Hardware/Latte_IRQ_Controller|Latte_IRQ_Controller]] (per-core)|drs=12}}
 +
{{rld|0x0d800444|32|LT_INTSR_AHBLT_PPC0}}
 +
{{rld|0x0d800448|32|LT_INTMR_AHBALL_PPC0}}
 +
{{rld|0x0d80044c|32|LT_INTMR_AHBLT_PPC0}}
 +
{{rld|0x0d800450|32|LT_INTSR_AHBALL_PPC1}}
 +
{{rld|0x0d800454|32|LT_INTSR_AHBLT_PPC1}}
 +
{{rld|0x0d800458|32|LT_INTMR_AHBALL_PPC1}}
 +
{{rld|0x0d80045c|32|LT_INTMR_AHBLT_PPC1}}
 +
{{rld|0x0d800460|32|LT_INTSR_AHBALL_PPC2}}
 +
{{rld|0x0d800464|32|LT_INTSR_AHBLT_PPC2}}
 +
{{rld|0x0d800468|32|LT_INTMR_AHBALL_PPC2}}
 +
{{rld|0x0d80046c|32|LT_INTMR_AHBLT_PPC2}}
 +
{{rld|0x0d800470|32|LT_INTSR_ARM_OLD|Old mirror?}}
 +
{{rld|0x0d800474|32|LT_GPIO_INTFLAG_OLD|Old mirror?}}
 +
{{rld|0x0d800478|32|LT_INTMR_ARM_OLD|Old mirror?}}
 +
{{rld|0x0d80047c|32|LT_GPIO_INTMASK_OLD|Old mirror?}}
 +
{{rld|0x0d800480|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800484|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004a4|32|LT_SYSPROTDRV2_UNK1|System protection driver (mirror?)|drs=2}}
 +
{{rld|0x0d8004a8|32|LT_SYSPROTDRV2_UNK1}}
 +
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800510|32|LT_PANIC_UNK|Something for panic}}
 
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
 
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
 
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}
 
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}
Line 78: Line 138:  
{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
 
{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
 +
{{rld|0x0d800570|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800574|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800578|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80057c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800580|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800584|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005a0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005a4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005b0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005b8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005bc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005c8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005e4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005e0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005ec|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800620|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800624|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800660|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800708|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8b4226|16|MEM_UNK1|Unknown}}
 
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
 
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
 
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
 
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
 +
{{rld|0x0d8b42c4|16|MEM_UNK2|Unknown}}
 +
{{rld|0x0d8b42c6|16|MEM_UNK3|Unknown}}
 +
{{rld|0x0d8b4300|16|MEM_UNK4|Unknown}}
 +
{{rld|0x0d8b4302|16|MEM_UNK5|Unknown}}
 
|}
 
|}
    
== General Registers ==
 
== General Registers ==
 +
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
 +
|16          |
 +
|U            |
 +
|            ||
 +
|8|4    |4    |
 +
|U|R    |R    |
 +
| |VERHI|VERLO|
 +
}}
 +
This register contains the hardware revision of the Latte chipset. The IOSU also stores this value in a flag inside it's kernel's heap.<br>
 +
Hardware revision -> IOSU equivalent flag<br>
 +
0x00 -> 0x00000001<br>
 +
0x10 -> 0x10000001<br>
 +
0x11 -> 0x10100001 or 0x10100008 or 0x1010000C<br>
 +
0x20 -> 0x20000001<br>
 +
0x21 -> 0x20100001
 +
{{regdesc
 +
|VERHI|Version
 +
|VERLO|Revision
 +
}}
 +
 
{{reg32 | LT_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 4 |
 
{{reg32 | LT_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 4 |
 
|16        |
 
|16        |
Hykem
108

edits

Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/1446"