Line 50:
Line 50:
{{rld|0x0d8001f0|32|LT_OTPDATA}}
{{rld|0x0d8001f0|32|LT_OTPDATA}}
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
+
{{rld|0x0d800400|32|LT_IPC_PPC0_PPCMSG|[[Hardware/IPC|IPC]] (per-core)|drs=12}}
+
{{rld|0x0d800404|32|LT_IPC_PPC0_PPCCTRL}}
+
{{rld|0x0d800408|32|LT_IPC_PPC0_ARMMSG}}
+
{{rld|0x0d80040c|32|LT_IPC_PPC0_ARMCTRL}}
+
{{rld|0x0d800410|32|LT_IPC_PPC1_PPCMSG}}
+
{{rld|0x0d800414|32|LT_IPC_PPC1_PPCCTRL}}
+
{{rld|0x0d800418|32|LT_IPC_PPC1_ARMMSG}}
+
{{rld|0x0d80041c|32|LT_IPC_PPC1_ARMCTRL}}
+
{{rld|0x0d800420|32|LT_IPC_PPC2_PPCMSG}}
+
{{rld|0x0d800424|32|LT_IPC_PPC2_PPCCTRL}}
+
{{rld|0x0d800428|32|LT_IPC_PPC2_ARMMSG}}
+
{{rld|0x0d80042c|32|LT_IPC_PPC2_ARMCTRL}}
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}