WiiUBrew

Changes

Hardware/Latte registers (view source)

Revision as of 23:10, 9 April 2023

390 bytes added ,  23:10, 9 April 2023
Sync with wiibrew
Line 37: Line 37:  
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
 
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
 
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
 
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
−
<!-- check: are these really Latte-only? -->
+
{{rld|0x0d800068|32|HW_I2CIOPINTEN|[[Hardware/Latte I²C|IOP I²C]] (used for the AV encoder)|drs=2}}
−
{{rld|0x0d800068|32|LT_AVE_I2C_INT_MASK{{check}}|[[Hardware/Latte I²C|Latte I²C]] (AV encoder)|drs=2}}
+
{{rld|0x0d80006c|32|HW_I2CIOPINTSTS}}
−
{{rld|0x0d80006c|32|LT_AVE_I2C_INT_STATE}}
+
{{rld|0x0d800070|32|HW_AIPPROT|[[Hardware/EXI|EXI]] access control}}
−
{{rld|0x0d800070|32|HW_AIP_PROT|[[Hardware/EXI|EXI]] access control}}
+
{{rld|0x0d800074|32|HW_AIPIOCTRL|Unknown}}
−
{{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}}
+
{{rld|0x0d800078|32|HW_VIINTEN|}}
 +
{{rld|0x0d80007c|32|HW_VIINTSTS|}}
 
{{rld|0x0d800080|32|HW_USBDBG0|USB related|drs=4}}
 
{{rld|0x0d800080|32|HW_USBDBG0|USB related|drs=4}}
 
{{rld|0x0d800084|32|HW_USBDBG1}}
 
{{rld|0x0d800084|32|HW_USBDBG1}}
Line 86: Line 87:  
{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
 
{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
 
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
 
{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
−
{{rld|0x0d800180|32|HW_DIRSTB|Drive interface resets}}
+
{{rld|0x0d800150|32|HW_I2CSCTRL}}
−
{{rld|0x0d800184|32|HW_MEMRSTB|Memory resets}}
+
{{rld|0x0d800154|32|HW_I2CSSTS}}
−
{{rld|0x0d800188|32|HW_SPARE0|Unknown}}
+
{{rld|0x0d800158|32|HW_I2CSRDEN}}
 +
{{rld|0x0d800160|32|HW_I2CSTRAP}}
 +
{{rld|0x0d800164|32|HW_I2CSCTRL}}
 +
{{rld|0x0d800168|32|HW_I2CSVISETYUV}}
 +
{{rld|0x0d80016c|32|HW_I2CSVISETFILT}}
 +
{{rld|0x0d800170|32|HW_SPARE2}}
 +
{{rld|0x0d800174|32|HW_SPARE3}}
 +
{{rld|0x0d800180|32|HW_COMPAT|Drive interface resets}}
 +
{{rld|0x0d800184|32|HW_RSTAHB|Memory resets}}
 +
{{rld|0x0d800188|32|HW_SPARE0|}}
 
{{rla|0x0d80018c|32|HW_SPARE1|Maps boot0 and controls a few other things}}
 
{{rla|0x0d80018c|32|HW_SPARE1|Maps boot0 and controls a few other things}}
−
{{rld|0x0d800190|32|HW_CLOCKS|Clock information}}
+
{{rld|0x0d800190|32|HW_SYSCTRL|System control}}
−
{{rld|0x0d800194|32|HW_RSTB|System resets}}
+
{{rld|0x0d800194|32|HW_RSTCTRL|Reset control}}
−
{{rld|0x0d800198|32|HW_IFPWRCTRL|Interface power control}}
+
{{rld|0x0d800198|32|HW_CLKGATE|Clock gating}}
−
{{rld|0x0d80019c|32|HW_PLLDR|PLL registers|drs=13}}
+
{{rld|0x0d80019c|32|HW_PLLDR|PLL registers|drs=16}}
−
{{rld|0x0d8001a8|32|UNKNOWN}}
+
{{rld|0x0d8001a0|32|HW_PLLSYSEXT1}}
 +
{{rld|0x0d8001a4|32|HW_PLLSYSEXT2}}
 +
{{rld|0x0d8001a8|32|HW_PLLAIEXT1}}
 +
{{rld|0x0d8001ac|32|HW_PLLATEXT2}}
 
{{rld|0x0d8001b0|32|HW_PLLSYS}}
 
{{rld|0x0d8001b0|32|HW_PLLSYS}}
 
{{rld|0x0d8001b4|32|HW_PLLSYSEXT}}
 
{{rld|0x0d8001b4|32|HW_PLLSYSEXT}}
Line 110: Line 123:  
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
 
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
 
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL|Clock power strength control}}
 
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL|Clock power strength control}}
−
{{rld|0x0d8001ec|32|HW_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
+
{{rld|0x0d8001ec|32|HW_EFUSEADDR|[[Hardware/OTP|OTP]]|drs=2}}
−
{{rld|0x0d8001f0|32|HW_OTPDATA}}
+
{{rld|0x0d8001f0|32|HW_EFUSEDATA}}
 
{{rld|0x0d8001f4|32|HW_DBGCLK|External debugger|drs=4}}
 
{{rld|0x0d8001f4|32|HW_DBGCLK|External debugger|drs=4}}
 
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
 
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
Line 121: Line 134:  
{{rld|0x0d800210|32|HW_SIINT}}
 
{{rld|0x0d800210|32|HW_SIINT}}
 
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 +
{{rla|0x0d800218|32|HW_DBGBUSRD|}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
−
<!-- check: are these really Latte-only? -->
+
{{rld|0x0d800250|32|HW_AVE_I2C_CLOCK{{check}}|[[Hardware/Latte I²C|AV encoder I²C]]|drs=4}}
−
{{rld|0x0d800250|32|LT_AVE_I2C_CLOCK{{check}}|[[Hardware/Latte I²C|Latte I²C]] (AV encoder)|drs=4}}
+
{{rld|0x0d800254|32|HW_AVE_I2C_INOUT_DATA}}
−
{{rld|0x0d800254|32|LT_AVE_I2C_INOUT_DATA}}
+
{{rld|0x0d800258|32|HW_AVE_I2C_INOUT_CTRL}}
−
{{rld|0x0d800258|32|LT_AVE_I2C_INOUT_CTRL}}
+
{{rld|0x0d80025c|32|HW_AVE_I2C_INOUT_SIZE}}
−
{{rld|0x0d80025c|32|LT_AVE_I2C_INOUT_SIZE}}
   
{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
 
{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
Line 169: Line 182:  
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
−
{{rla|0x0d800510|32|LT_OTPPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each)}}
+
{{rla|0x0d800510|32|LT_EFUSEPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each)}}
 
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for Wood}}
 
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for Wood}}
 
{{rld|0x0d800520|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
 
{{rld|0x0d800520|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
Line 187: Line 200:  
{{rld|0x0d800558|32|LT_GPIO_STRAPS}}
 
{{rld|0x0d800558|32|LT_GPIO_STRAPS}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER}}
−
{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK|[[Hardware/Latte I²C|Latte I²C]] (SMC)|drs=6}}
+
{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK|[[Hardware/Latte I²C|SMC I²C]]|drs=6}}
 
{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
 
{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
 
{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
 
{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
Line 202: Line 215:  
{{rld|0x0d8005c8|32|LT_IOSTRCTRL2|I/O power strength control}}
 
{{rld|0x0d8005c8|32|LT_IOSTRCTRL2|I/O power strength control}}
 
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
−
{{rld|0x0d8005e0|32|LT_RSTB|System resets}}
+
{{rld|0x0d8005e0|32|LT_SYSCTRL|System control}}
−
{{rld|0x0d8005e4|32|LT_MEMRSTB|Memory resets}}
+
{{rld|0x0d8005e4|32|LT_RSTCTRL|Reset control}}
−
{{rld|0x0d8005e8|32|LT_IFPWRCTRL|Interface power control}}
+
{{rld|0x0d8005e8|32|LT_CLKGATE|Clock gating}}
 
{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
 
{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
 
{{rla|0x0d800620|32|LT_ABIF_ADDR|ASIC bus interface|drs=2}}
 
{{rla|0x0d800620|32|LT_ABIF_ADDR|ASIC bus interface|drs=2}}
Line 326: Line 339:  
}}
 
}}
   −
{{reg32 | LT_OTPPROT | addr = 0x0d800510 | hifields = 2 | lofields = 1 |
+
{{reg32 | LT_EFUSEPROT | addr = 0x0d800510 | hifields = 2 | lofields = 1 |
 
|4      |12  |
 
|4      |12  |
 
|R/W    |?    |
 
|R/W    |?    |
Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/3585"