Hardware/Latte registers

Latte registers
Access
Espresso	Partial
Starbuck	Full
Registers
Base	0x0d800000
Length	???
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	12
Latte	0,10,11,17,30,31,...[check]

The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the Espresso. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.

Registers with the HW_* prefix (known officially as ACR registers) are used both by Wood (Hollywood/Bollywood) and Latte hardware. Registers with the LT_* prefix (known officially as CCR registers) are exclusive to Latte hardware.

Register list

Latte Registers
Address	Bits	Name	Description
0x0d800000	32	HW_IPCPPCMSG	Wood IPC
0x0d800004	32	HW_IPCPPCCTRL
0x0d800008	32	HW_IPCIOPMSG
0x0d80000c	32	HW_IPCIOPCTRL
0x0d800010	32	HW_TIMER	CPU timer
0x0d800014	32	HW_ALARM
0x0d800018	32	HW_VI1CFG	VI configuration
0x0d80001c	32	HW_VIDIM	VI dimmer
0x0d800024	32	HW_VISOLID	VI solid color
0x0d800030	32	HW_PPCINTSTS	Wood IRQs
0x0d800034	32	HW_PPCINTEN
0x0d800038	32	HW_IOPINTSTS
0x0d80003c	32	HW_IOPIRQINTEN
0x0d800040	32	HW_IOPFIQINTEN
0x0d800044	32	HW_IOPINTPPC	Unknown
0x0d800048	32	HW_WDGINTSTS	Watchdog interrupt status
0x0d80004c	32	HW_WDGCFG	Watchdog configuration
0x0d800050	32	HW_DMAADRINTSTS	DMA transfer interrupt status
0x0d800054	32	HW_CPUADRINTSTS	CPU transfer interrupt status
0x0d800058	32	HW_DBGINTSTS	Debug interrupt status
0x0d80005c	32	HW_DBGINTEN	Debug interrupt enable
0x0d800060	32	HW_SRNPROT	SRAM access control
0x0d800064	32	HW_BUSPROT	AHB access control
0x0d800068	32	HW_I2CIOPINTEN	I2C interrupt enable
0x0d80006c	32	HW_I2CIOPINTSTS	I2C interrupt status
0x0d800070	32	HW_AIPPROT	EXI access control
0x0d800074	32	HW_AIPIOCTRL	Unknown
0x0d800078	32	HW_VIINTEN	VI interrupt enable
0x0d80007c	32	HW_VIINTSTS	VI interrupt status
0x0d800080	32	HW_USBDBG0	USB related
0x0d800084	32	HW_USBDBG1
0x0d800088	32	HW_USBFRCRST
0x0d80008c	32	HW_USBIOTEST
0x0d800090	32	HW_ELAREGADDR	CoreSight ELA
0x0d800094	32	HW_ELAREGDATA
0x0d800098	32	HW_MEMTSTN
0x0d80009c	32	HW_MEMTSTP
0x0d8000c0	32	HW_GPIOPPCOUT	Wood GPIOs
0x0d8000c4	32	HW_GPIOPPCDIR
0x0d8000c8	32	HW_GPIOPPCIN
0x0d8000cc	32	HW_GPIOPPCINTLVL
0x0d8000d0	32	HW_GPIOPPCINTSTS
0x0d8000d4	32	HW_GPIOPPCINTEN
0x0d8000d8	32	HW_GPIOPPCSTRAPS
0x0d8000dc	32	HW_GPIOIOPEN
0x0d8000e0	32	HW_GPIOIOPOUT
0x0d8000e4	32	HW_GPIOIOPDIR
0x0d8000e8	32	HW_GPIOIOPIN
0x0d8000ec	32	HW_GPIOIOPINTLVL
0x0d8000f0	32	HW_GPIOIOPINTSTS
0x0d8000f4	32	HW_GPIOIOPINTEN
0x0d8000f8	32	HW_GPIOIOPSTRAPS
0x0d8000fc	32	HW_GPIOIOPPPCOWNER
0x0d800100	32	HW_ARBCFGM0	AHB arbiter configuration
0x0d800104	32	HW_ARBCFGM1
0x0d800108	32	HW_ARBCFGM2
0x0d80010c	32	HW_ARBCFGM3
0x0d800110	32	HW_ARBCFGM4
0x0d800114	32	HW_ARBCFGM5
0x0d800118	32	HW_ARBCFGM6
0x0d80011c	32	HW_ARBCFGM7
0x0d800120	32	HW_ARBCFGM8
0x0d800124	32	HW_ARBCFGM9
0x0d800128	32	HW_ARBCFGMA
0x0d80012c	32	HW_ARBCFGMB
0x0d800130	32	HW_ARBCFGMC
0x0d800134	32	HW_ARBCFGMD
0x0d800138	32	HW_ARBCFGME
0x0d80013c	32	HW_ARBCFGMF
0x0d800140	32	HW_ARBCFGCPU
0x0d800144	32	HW_ARBCFGDMA
0x0d800148	32	HW_ARBPCNTCFG
0x0d80014c	32	HW_ARBPCNTSTS
0x0d800150	32	HW_I2CSCTRL	I2C slave (VI)
0x0d800154	32	HW_I2CSSTS
0x0d800158	32	HW_I2CSRDEN
0x0d800160	32	HW_I2CSGAMMA
0x0d800164	32	HW_I2CSTRAP
0x0d800168	32	HW_I2CSVISETYUV
0x0d80016c	32	HW_I2CSVISETFILT
0x0d800170	32	HW_SPARE2	Unknown
0x0d800174	32	HW_SPARE3	Unknown
0x0d800180	32	HW_COMPAT	Drive interface resets
0x0d800184	32	HW_RSTAHB	AHB reset control
0x0d800188	32	HW_SPARE0	Unknown
0x0d80018c	32	HW_SPARE1	Maps boot0 and controls a few other things
0x0d800190	32	HW_SYSCTRL	System control
0x0d800194	32	HW_RSTCTRL	Reset control
0x0d800198	32	HW_CLKGATE	Clock gating
0x0d80019c	32	HW_PLLDR	PLL registers
0x0d8001a0	32	HW_PLLSYSEXT1
0x0d8001a4	32	HW_PLLSYSEXT2
0x0d8001a8	32	HW_PLLAIEXT1
0x0d8001ac	32	HW_PLLATEXT2
0x0d8001b0	32	HW_PLLSYS
0x0d8001b4	32	HW_PLLSYSEXT
0x0d8001b8	32	HW_PLLDSK
0x0d8001bc	32	HW_PLLDDR
0x0d8001c0	32	HW_PLLDDREXT
0x0d8001c4	32	HW_PLLVI
0x0d8001c8	32	HW_PLLVIEXT
0x0d8001cc	32	HW_PLLAI
0x0d8001d0	32	HW_PLLAIEXT
0x0d8001d4	32	HW_PLLUSB
0x0d8001d8	32	HW_PLLUSBEXT
0x0d8001dc	32	HW_IOPWRCTRL	I/O power control
0x0d8001e0	32	HW_IOSTRCTRL0	I/O power strength control
0x0d8001e4	32	HW_IOSTRCTRL1	I/O power strength control
0x0d8001e8	32	HW_CLKSTRCTRL	Clock power strength control
0x0d8001ec	32	HW_EFUSEADDR	OTP
0x0d8001f0	32	HW_EFUSEDATA
0x0d8001f4	32	HW_DBGCLK	External debugger
0x0d8001f8	32	HW_OBSCLKOCTRL
0x0d8001fc	32	HW_OBSCLKICTRL
0x0d800200	32	HW_DBGPORT
0x0d800204	32	HW_SICLKDIV	SI related
0x0d800208	32	HW_SICTRL
0x0d80020c	32	HW_SIDATA
0x0d800210	32	HW_SIINT
0x0d800214	32	HW_CHIPREVID	Hardware version (Wood)
0x0d800218	32	HW_DBGBUSRD	Debug bus read value
0x0d800224	32	UNKNOWN	Unknown
0x0d800250	32	HW_I2CMCTRL	I2C master (A/V encoder)
0x0d800254	32	HW_I2CMDATAWR
0x0d800258	32	HW_I2CMWREN
0x0d80025c	32	HW_I2CMDATARD
0x0d800400	32	LT_IPCPPCMSG0	Latte IPC (per-core)
0x0d800404	32	LT_IPCPPCCTRL0
0x0d800408	32	LT_IPCIOPMSG0
0x0d80040c	32	LT_IPCIOPCTRL0
0x0d800410	32	LT_IPCPPCMSG1
0x0d800414	32	LT_IPCPPCCTRL1
0x0d800418	32	LT_IPCIOPMSG1
0x0d80041c	32	LT_IPCIOPCTRL1
0x0d800420	32	LT_IPCPPCMSG2
0x0d800424	32	LT_IPCPPCCTRL2
0x0d800428	32	LT_IPCIOPMSG2
0x0d80042c	32	LT_IPCIOPCTRL2
0x0d800440	32	LT_PPC0INTSTSALL	Latte IRQs (per-core)
0x0d800444	32	LT_PPC0INTSTSLATTE
0x0d800448	32	LT_PPC0INTENALL
0x0d80044c	32	LT_PPC0INTENLATTE
0x0d800450	32	LT_PPC1INTSTSALL
0x0d800454	32	LT_PPC1INTSTSLATTE
0x0d800458	32	LT_PPC1INTENALL
0x0d80045c	32	LT_PPC1INTENLATTE
0x0d800460	32	LT_PPC2INTSTSALL
0x0d800464	32	LT_PPC2INTSTSLATTE
0x0d800468	32	LT_PPC2INTENALL
0x0d80046c	32	LT_PPC2INTENLATTE
0x0d800470	32	LT_IOPINTSTSALL
0x0d800474	32	LT_IOPINTSTSLATTE
0x0d800478	32	LT_IOPIRQINTENALL
0x0d80047c	32	LT_IOPIRQINTENLATTE
0x0d800480	32	LT_IOPFIQINTENALL
0x0d800484	32	LT_IOPFIQINTENLATTE
0x0d8004a0	32	LT_WDG2INTSTS	Watchdog interrupt status
0x0d8004a4	32	LT_DMAADR2INTSTS	DMA transfer interrupt status
0x0d8004a8	32	LT_CPUADR2INTSTS	CPU transfer interrupt status
0x0d8004c0	32	LT_ARBCFGM0	AHB arbiter configuration
0x0d8004c4	32	LT_ARBCFGM1
0x0d8004c8	32	LT_ARBCFGM2
0x0d8004cc	32	LT_ARBCFGM3
0x0d8004d0	32	LT_ARBCFGM4
0x0d8004d4	32	LT_ARBCFGM5
0x0d8004d8	32	LT_ARBCFGM6
0x0d8004dc	32	LT_ARBCFGM7
0x0d8004e0	32	LT_ARBCFGM8
0x0d8004e4	32	LT_ARBCFGM9
0x0d800500	32	LT_PPCBUSPROT	AHB access control for the PPC
0x0d800504	32	LT_IOPBUSPROT	AHB access control for the IOP
0x0d800510	32	LT_EFUSEPROT	OTP access control
0x0d800514	32	LT_SYSPROT	Hardware sandbox for Wood
0x0d800520	32	LT_GPIOPPCOUT	Latte GPIOs
0x0d800524	32	LT_GPIOPPCDIR
0x0d800528	32	LT_GPIOPPCIN
0x0d80052c	32	LT_GPIOPPCINTLVL
0x0d800530	32	LT_GPIOPPCINTSTS
0x0d800534	32	LT_GPIOPPCINTEN
0x0d800538	32	LT_GPIOPPCSTRAPS
0x0d80053c	32	LT_GPIOIOPEN
0x0d800540	32	LT_GPIOIOPOUT
0x0d800544	32	LT_GPIOIOPDIR
0x0d800548	32	LT_GPIOIOPIN
0x0d80054c	32	LT_GPIOIOPINTLVL
0x0d800550	32	LT_GPIOIOPINTSTS
0x0d800554	32	LT_GPIOIOPINTEN
0x0d800558	32	LT_GPIOIOPSTRAPS
0x0d80055c	32	LT_GPIOIOPPPCOWNER
0x0d800570	32	LT_I2CMCTRL	I2C master (SMC)
0x0d800574	32	LT_I2CMDATAWR
0x0d800578	32	LT_I2CMWREN
0x0d80057c	32	LT_I2CMDATARD
0x0d800580	32	LT_I2CIOPINTEN	I2C interrupt status
0x0d800584	32	LT_I2CIOPINTSTS	I2C interrupt enable
0x0d8005a0	32	LT_CHIPREVID	Hardware version (Latte)
0x0d8005a4	32	LT_SYSCFG1	System configuration
0x0d8005b0	32	LT_PIMEMCOMPAT	Processor interface memory bus compat mode for Wood
0x0d8005b4	32	LT_AHBCOMPAT	AHB compat mode for Wood
0x0d8005b8	32	LT_AICOMPAT	AI compat mode for Wood
0x0d8005bc	32	LT_IOP2XCTRL	IOP clock multiplier control
0x0d8005c0	32	LT_EXICOMPAT	EXI compat mode for Wood
0x0d8005c4	32	LT_IOPWRCTRL	I/O power control
0x0d8005c8	32	LT_IOSTRCTRL0	I/O power strength control
0x0d8005cc	32	LT_IOSTRCTRL1	I/O power strength control
0x0d8005e0	32	LT_RSTCTRL	Reset control
0x0d8005e4	32	LT_RSTAHB	AHB reset control
0x0d8005e8	32	LT_CLKGATE	Clock gating
0x0d8005ec	32	LT_CLKCTRL	Clock control
0x0d800620	32	LT_ABIFADDR	ASIC bus interface
0x0d800624	32	LT_ABIFDATA
0x0d800628	32	UNKNOWN	Unknown
0x0d800640	32	LT_PIMEMCFG	Processor interface memory bus configuration
0x0d800660	32	LT_SATACFG	SATA configuration
0x0d800664	32	UNKNOWN	Unknown
0x0d800668	32	UNKNOWN	Unknown (bitmask 0x0FFFFFFF)
0x0d80066c	32	UNKNOWN	Unknown (bitmask 0x0FFFFFFF)
0x0d800670	32	UNKNOWN	Unknown (bitmask 0x0FFFFFFF)
0x0d80067c	32	UNKNOWN	Unknown (bitmask 0x3f00ff00)
0x0d8006a0	32	LT_DMCUDATAWR	DMCU data write (bitmask 0x0FFFFFFF)
0x0d8006a4	32	LT_DMCUDATARD	DMCU data read (bitmask 0x0FFFFFFF)
0x0d8006a8	32	LT_DMCUCTRL	DMCU control register (bitmask 0x80000001)
0x0d800700	32	LT_SPARE0	Unknown (bitmask 0x7FFFFFFF)
0x0d800704	32	LT_SPARE1	Unknown (bitmask 0x7F7FFFFF)
0x0d800708	32	LT_SPARE2	DC compat mode for Wood (bitmask 0x7FFFFFFF)
0x0d80070c	32	LT_SPARE3	Unknown (bitmask 0x7FFFFFFF)

General Registers

HW_RSTAHB (0x0d800184)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?									R/W	?
Field										RSTB_AHM

Field	Description
RSTB_AHM	AHM reset.

HW_SPARE1 (0x0d80018c)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?	R/W	?	R/W	?
Field		RSTB_DCPL_GFXPI		BOOT0

Field	Description
BOOT0	Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on HW_SRNPROT.
RSTB_DCPL_GFXPI	DCPL GFX PI reset.

HW_RSTCTRL (0x0d800194)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	U					R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Field						NLCKB_EDRAM	RSTB_EDRAM	RSTB_AHB	RSTB_IOP	RSTB_DSP	RSTB_VI1	RSTB_VI	RSTB_IOPI	RSTB_IOMEM	RSTB_IODI	RSTB_IOEXI
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Field	RSTB_IOSI	RSTB_AI_I2S3	RSTB_GFX	RSTB_GFXTCPE	RSTB_MEM	RSTB_DIRSTB	RSTB_PI	RSTB_MEMRSTB	NLCKB_SYSPLL	RSTB_SYSPLL	SRSTB_CPU	RSTB_CPU	RSTB_DSKPLL	RSTB	CRSTB	RSTINB

Field	Description
NLCKB_EDRAM	Unlock external DRAM reset?
RSTB_EDRAM	External DRAM reset.
RSTB_AHB	IOP AHB reset.
RSTB_IOP	IOP reset.
RSTB_VI1	VI1 reset.
RSTB_VI	VI reset.
RSTB_IOPI	PI IO reset.
RSTB_IOMEM	MEM IO reset.
RSTB_IODI	DI IO reset.
RSTB_IOEXI	EXI IO reset.
RSTB_IOSI	SI IO reset.
RSTB_AI_I2S3	AI I2S3 reset.
RSTB_GFX	GFX reset.
RSTB_GFXTCPE	GFX TCPE reset.
RSTB_MEM	MEM reset.
RSTB_DIRSTB	DI reset.

Field	Description
NLCKB_SYSPLL	Unlock SYSPLL reset?
RSTB_SYSPLL	SYSPLL reset.
SRSTB_CPU	PowerPC SRESET.
RSTB_CPU	PowerPC HRESET.
RSTB_DSKPLL	DSKPLL reset.
RSTB	Reset.
CRSTB	CPU reset?
RSTINB	System reset.

HW_CLKGATE (0x0d800198)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?									R/W	?
Field										GFX
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?	R/W	?
Field		VI

Field	Description
GFX	GFX clock gate.
VI	VI clock gate.

HW_IOPWRCTRL (0x0d8001dc)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?		?		R/W		R/W		R/W		R/W		R/W		?
Field					GPIO		GPIO		FLA		SDIO		SI
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?		R/W		?		R/W		R/W		?		?		?
Field			AI				VI		DI

HW_IOSTRCTRL0 (0x0d8001e0)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?		?			?			R/W			R/W			?
Field									VI			DI
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?	?			?			R/W			?			R/W
Field								SI						AI

Field	Description
VI	Video Interface IO power control. IOSU sets to 0x3 on Hollywood hardware, or 0x1 on Bollywood or Latte hardware.
DI	Drive Interface IO power control. IOSU sets to 0x1 on Hollywood hardware, or 0x2 on Bollywood or Latte hardware.
SI	Serial Interface IO power control. IOSU sets to 0x1 on Hollywood and Bollywood chipsets, 0x2 on Latte chips.
AI	Audio Interface IO power control. IOSU sets to 0x2 on Hollywood hardware, or 0x1 on Bollywood or Latte hardware.

HW_DBGPORT (0x0d800200)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?					R/W
Field						DBG_ID
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	R/W	?
Field	DBGPORT_BIT15															GPIO_EN

This seems to select internal debug values to be viewed in HW_DBGBUSRD, as well as external GPIOs if GPIO_EN is set. Values are split by u16s.

Field	Description
DBG_ID	Selects the values outputted to the low and high HW_DBGBUSRD u16s.
DBGPORT_BIT15	Mirrors the upper u16 in HW_DBGBUSRD to the lower u16.
GPIO_EN	Outputs {HW_DBGBUSRD[11:8], HW_DBGBUSRD[15:12]} to NDEV_LED (and other GPIOs?)

HW_CHIPREVID (0x0d800214)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	U
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	U								R				R
Field									VERHI				VERLO

This register contains the hardware revision of the Wood chipset (used for vWii mode).

IOS-BSP maps these values to hardware versions as follows:

Value	HardwareVersion	Description
0x00	0x00000000	BSP_HARDWARE_VERSION_UNKNOWN
0x00	0x00000001	BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_1
0x10	0x10000001	BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_2
0x11	0x10100001	BSP_HARDWARE_VERSION_HOLLYWOOD_PROD_FOR_WII
0x11	0x10100008	BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO
0x11	0x1010000C	BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO_ESPRESSO
0x20	0x20000001	BSP_HARDWARE_VERSION_BOLLYWOOD
0x21	0x20100001	BSP_HARDWARE_VERSION_BOLLYWOOD_PROD_FOR_WII

Field	Description
VERHI	Version.
VERLO	Revision.

LT_EFUSEPROT (0x0d800510)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	R/W
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	R/W
Field

This register is a bitmask for locking out chunks of the OTP. Each bit clears out 0x20 bytes of the OTP starting from the bottom (bank 7 is 0xF0000000) to the top (bank 0 is 0x0000000F).

LT_CHIPREVID (0x0d8005a0)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	R
Field	MAGIC
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	U								R				R
Field									VERHI				VERLO

This register contains the hardware revision of the Latte chipset.

IOS-BSP maps these values to hardware versions as follows:

Value	HardwareVersion	Description
0x10	0x21100010	BSP_HARDWARE_VERSION_LATTE_A11_EV
0x10	0x21100020	BSP_HARDWARE_VERSION_LATTE_A11_CAT
0x18	0x21200010	BSP_HARDWARE_VERSION_LATTE_A12_EV
0x18	0x21200020	BSP_HARDWARE_VERSION_LATTE_A12_CAT
0x21	0x22100010	BSP_HARDWARE_VERSION_LATTE_A2X_EV
0x21	0x22100020	BSP_HARDWARE_VERSION_LATTE_A2X_CAT
0x30	0x23100010	BSP_HARDWARE_VERSION_LATTE_A3X_EV
0x30	0x23100020	BSP_HARDWARE_VERSION_LATTE_A3X_CAT
0x30	0x23100028	BSP_HARDWARE_VERSION_LATTE_A3X_CAFE
0x40	0x24100010	BSP_HARDWARE_VERSION_LATTE_A4X_EV
0x40	0x24100020	BSP_HARDWARE_VERSION_LATTE_A4X_CAT
0x40	0x24100028	BSP_HARDWARE_VERSION_LATTE_A4X_CAFE
0x50	0x25100010	BSP_HARDWARE_VERSION_LATTE_A5X_EV
0x50	0x25100011	BSP_HARDWARE_VERSION_LATTE_A5X_EV_Y
0x50	0x25100020	BSP_HARDWARE_VERSION_LATTE_A5X_CAT
0x50	0x25100028	BSP_HARDWARE_VERSION_LATTE_A5X_CAFE
0x60	0x26100010	BSP_HARDWARE_VERSION_LATTE_B1X_EV
0x60	0x26100011	BSP_HARDWARE_VERSION_LATTE_B1X_EV_Y
0x60	0x26100020	BSP_HARDWARE_VERSION_LATTE_B1X_CAT
0x60	0x26100028	BSP_HARDWARE_VERSION_LATTE_B1X_CAFE

Field	Description
MAGIC	Hardcoded to 0xCAFE.
VERHI	Version.
VERLO	Revision.

LT_SYSCFG1 (0x0d8005a4)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	R/W	?
Field	DBG_HALT
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?												R/W	R/W	R/W	?
Field													CMPT_RETSTAT1	CMPT_RETSTAT0	SLC_EMU

Field	Description
DBG_HALT	Halts the IOSU's boot sequence and waits for user input from JTAG.
SLC_EMU	Emulate SLC on host.

LT_PIMEMCOMPAT (0x0d8005b0)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?										R/W	?
Field											PPC_COMPAT

Field	Description
PPC_COMPAT	If set, PPC clocks are 3x SYSPLL. If unset, PPC clocks are 5x SYSPLL. In IOSU, this bit is set based on SEEPROM's ppcClockMultiplier value.

LT_RSTCTRL (0x0d8005e0)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?												R/W	?
Field													RTSB_AI_I2S5

Field	Description
RTSB_AI_I2S5	AI I2S5 reset.

LT_RSTAHB (0x0d8005e4)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?							R/W	?	R/W	?
Field								RTSB_DI2SATA		RTSB_AHMN

Field	Description
RTSB_DI2SATA	DI2SATA reset.
RTSB_AHMN	AHMN reset.

LT_ABIFADDR (0x0d800620)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	R/W		R/W						R/W
Field	tile_id		device						offset
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	R/W
Field	offset

The ASIC bus interface register indexes a set of registers. The GPU device seems to be the same as the registers at 0x0C200000 (ex: offset 0xF55C maps to 0x0C20F55C).

Field	Description
tile_id	See below
device	See below
offset	Offset into registers, acccessed through LT_ABIFDATA.

tile_id/device values:

Tile	Device	Description
0x0	0x0	CplCt (Center?)
0x0	0x1	CplTr (Top-right?)
0x0	0x2	CplTl (Top-left?)
0x0	0x3	CplBr (Bottom-right?)
0x0	0x4	CplBl (Bottom-left?)
0x2	0x0	MEM1 mirror (addresses are reordered: 0xC = offset 0x0)
0x2	0x1	MEM1 mirror (0x01000000)
0x2	0x2	? (0xDEADBEEF)
0x3	0x0	GPU