In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

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Hardware/Latte registers (view source)

Revision as of 23:16, 7 December 2024

1,710 bytes added ,  23:16, 7 December 2024
no edit summary
Line 22: Line 22:  
{{rld|0x0d800018|32|HW_VI1CFG|VI configuration}}
 
{{rld|0x0d800018|32|HW_VI1CFG|VI configuration}}
 
{{rld|0x0d80001c|32|HW_VIDIM|VI dimmer}}
 
{{rld|0x0d80001c|32|HW_VIDIM|VI dimmer}}
 +
{{rld|0x0d800020|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800024|32|HW_VISOLID|VI solid color}}
 
{{rld|0x0d800024|32|HW_VISOLID|VI solid color}}
 +
{{rld|0x0d800028|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80002c|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800030|32|HW_PPCINTSTS|[[Hardware/Latte_IRQ_Controller|Wood IRQs]]|drs=5}}
 
{{rld|0x0d800030|32|HW_PPCINTSTS|[[Hardware/Latte_IRQ_Controller|Wood IRQs]]|drs=5}}
 
{{rld|0x0d800034|32|HW_PPCINTEN}}
 
{{rld|0x0d800034|32|HW_PPCINTEN}}
Line 135: Line 138:  
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rla|0x0d800218|32|HW_DBGBUSRD|Debug bus read value}}
 
{{rla|0x0d800218|32|HW_DBGBUSRD|Debug bus read value}}
 +
{{rld|0x0d80021c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800220|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800228|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80022c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800230|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800234|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800238|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80023c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800240|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800244|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800248|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80024c|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800250|32|HW_I2CMCTRL|[[Hardware/Latte I2C|I2C master]] (A/V encoder)|drs=4}}
 
{{rld|0x0d800250|32|HW_I2CMCTRL|[[Hardware/Latte I2C|I2C master]] (A/V encoder)|drs=4}}
 
{{rld|0x0d800254|32|HW_I2CMDATAWR}}
 
{{rld|0x0d800254|32|HW_I2CMDATAWR}}
 
{{rld|0x0d800258|32|HW_I2CMWREN}}
 
{{rld|0x0d800258|32|HW_I2CMWREN}}
 
{{rld|0x0d80025c|32|HW_I2CMDATARD}}
 
{{rld|0x0d80025c|32|HW_I2CMDATARD}}
 +
{{rld|0x0d800260|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800264|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800290|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800294|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800298|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80029c|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002a0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002a4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002a8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002ac|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002b0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002b4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002b8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002bc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002c0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002c4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002c8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002cc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8002d0|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800400|32|LT_IPCPPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800400|32|LT_IPCPPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800404|32|LT_IPCPPCCTRL0}}
 
{{rld|0x0d800404|32|LT_IPCPPCCTRL0}}
Line 170: Line 204:  
{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}
 
{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}
 
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE}}
 
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE}}
 +
{{rld|0x0d800488|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d80048c|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8004a0|32|LT_WDG2INTSTS|Watchdog interrupt status}}
 
{{rld|0x0d8004a0|32|LT_WDG2INTSTS|Watchdog interrupt status}}
 
{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|DMA transfer interrupt status}}
 
{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|DMA transfer interrupt status}}
Line 183: Line 219:  
{{rld|0x0d8004e0|32|LT_ARBCFGM8}}
 
{{rld|0x0d8004e0|32|LT_ARBCFGM8}}
 
{{rld|0x0d8004e4|32|LT_ARBCFGM9}}
 
{{rld|0x0d8004e4|32|LT_ARBCFGM9}}
 +
{{rld|0x0d8004e8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004ec|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004f0|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800500|32|LT_PPCBUSPROT|AHB access control for the PPC}}
 
{{rld|0x0d800500|32|LT_PPCBUSPROT|AHB access control for the PPC}}
 
{{rld|0x0d800504|32|LT_IOPBUSPROT|AHB access control for the IOP}}
 
{{rld|0x0d800504|32|LT_IOPBUSPROT|AHB access control for the IOP}}
Line 203: Line 242:  
{{rld|0x0d800558|32|LT_GPIOIOPSTRAPS}}
 
{{rld|0x0d800558|32|LT_GPIOIOPSTRAPS}}
 
{{rld|0x0d80055c|32|LT_GPIOIOPPPCOWNER}}
 
{{rld|0x0d80055c|32|LT_GPIOIOPPPCOWNER}}
 +
{{rld|0x0d800560|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800570|32|LT_I2CMCTRL|[[Hardware/Latte I2C|I2C master]] (SMC)|drs=4}}
 
{{rld|0x0d800570|32|LT_I2CMCTRL|[[Hardware/Latte I2C|I2C master]] (SMC)|drs=4}}
 
{{rld|0x0d800574|32|LT_I2CMDATAWR}}
 
{{rld|0x0d800574|32|LT_I2CMDATAWR}}
Line 211: Line 251:  
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
 
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
 
{{rla|0x0d8005a4|32|LT_SYSCFG1|System configuration}}
 
{{rla|0x0d8005a4|32|LT_SYSCFG1|System configuration}}
 +
{{rld|0x0d8005a8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8005ac|32|UNKNOWN|Unknown}}
 
{{rla|0x0d8005b0|32|LT_PIMEMCOMPAT|Processor interface memory bus compat mode for Wood}}
 
{{rla|0x0d8005b0|32|LT_PIMEMCOMPAT|Processor interface memory bus compat mode for Wood}}
 
{{rld|0x0d8005b4|32|LT_AHBCOMPAT|AHB compat mode for Wood}}
 
{{rld|0x0d8005b4|32|LT_AHBCOMPAT|AHB compat mode for Wood}}
Line 232: Line 274:  
{{rld|0x0d80066c|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
 
{{rld|0x0d80066c|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
 
{{rld|0x0d800670|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
 
{{rld|0x0d800670|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
 +
{{rld|0x0d800674|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d800678|32|UNKNOWN|Unknown}}
 
{{rld|0x0d80067c|32|UNKNOWN|Unknown (bitmask 0x3f00ff00)}}
 
{{rld|0x0d80067c|32|UNKNOWN|Unknown (bitmask 0x3f00ff00)}}
 +
{{rld|0x0d800680|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8006a0|32|LT_DMCUDATAWR|[[Hardware/DMCU|DMCU]] data write (bitmask 0x0FFFFFFF)}}
 
{{rld|0x0d8006a0|32|LT_DMCUDATAWR|[[Hardware/DMCU|DMCU]] data write (bitmask 0x0FFFFFFF)}}
 
{{rld|0x0d8006a4|32|LT_DMCUDATARD|[[Hardware/DMCU|DMCU]] data read (bitmask 0x0FFFFFFF)}}
 
{{rld|0x0d8006a4|32|LT_DMCUDATARD|[[Hardware/DMCU|DMCU]] data read (bitmask 0x0FFFFFFF)}}
Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/4101"

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