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Hardware/Latte registers (view source)
Revision as of 03:41, 11 February 2024
, 03:41, 11 February 2024no edit summary
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== Register list ==+{{reg32 | LT_EFUSEPROT | addr = 0x0d800510 | hifields = 1 | lofields = 1 |
−|16 |
−|R/W |
−| ||
−|16 |
−|R/W |
−| |
−}}
−This register is a bitmask for locking out chunks of the OTP. Each bit clears out 0x20 bytes of the OTP starting from the bottom (bank 7 is 0xF0000000) to the top (bank 0 is 0x0000000F).
−
Registers with the '''HW_*''' prefix (known officially as '''ACR''' registers) are used both by Wood (Hollywood/Bollywood) and Latte hardware. Registers with the '''LT_*''' prefix (known officially as '''CCR''' registers) are exclusive to Latte hardware.
Registers with the '''HW_*''' prefix (known officially as '''ACR''' registers) are used both by Wood (Hollywood/Bollywood) and Latte hardware. Registers with the '''LT_*''' prefix (known officially as '''CCR''' registers) are exclusive to Latte hardware.
−= Register List =
{{reglist|Latte Registers}}
{{reglist|Latte Registers}}
{{rld|0x0d800000|32|HW_IPCPPCMSG|[[Hardware/IPC|Wood IPC]]|drs=4}}
{{rld|0x0d800000|32|HW_IPCPPCMSG|[[Hardware/IPC|Wood IPC]]|drs=4}}
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{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL|Clock power strength control}}
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL|Clock power strength control}}
−{{rld|0x0d8001ec|32|HW_EFUSEADDR|[[Hardware/OTP|OTP]]|drs=2}}
+{{rld|0x0d8001ec|32|HW_EFUSEADDR|[[Hardware/eFuse|eFuse]]|drs=2}}
{{rld|0x0d8001f0|32|HW_EFUSEDATA}}
{{rld|0x0d8001f0|32|HW_EFUSEDATA}}
{{rld|0x0d8001f4|32|HW_DBGCLK|External debugger|drs=4}}
{{rld|0x0d8001f4|32|HW_DBGCLK|External debugger|drs=4}}
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{{rld|0x0d800500|32|LT_PPCBUSPROT|AHB access control for the PPC}}
{{rld|0x0d800500|32|LT_PPCBUSPROT|AHB access control for the PPC}}
{{rld|0x0d800504|32|LT_IOPBUSPROT|AHB access control for the IOP}}
{{rld|0x0d800504|32|LT_IOPBUSPROT|AHB access control for the IOP}}
−{{rla|0x0d800510|32|LT_EFUSEPROT|OTP access control}}
+{{rld|0x0d800510|32|LT_EFUSEPROT|[[Hardware/eFuse|eFuse]] access control}}
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for Wood}}
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for Wood}}
{{rld|0x0d800520|32|LT_GPIOPPCOUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
{{rld|0x0d800520|32|LT_GPIOPPCOUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
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|}
|}
−== General Registers ==
+= Register Details =
{{reg32 | HW_RSTAHB | addr = 0x0d800184 | hifields = 1 | lofields = 3 |
{{reg32 | HW_RSTAHB | addr = 0x0d800184 | hifields = 1 | lofields = 3 |
|16 |
|16 |
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|VERLO|Revision.
|VERLO|Revision.
}}
}}
−{{reg32 | LT_CHIPREVID | addr = 0x0d8005a0 | hifields = 1 | lofields = 3 |
{{reg32 | LT_CHIPREVID | addr = 0x0d8005a0 | hifields = 1 | lofields = 3 |