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→Register List
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+
==Register List==
==Register List==
−The Latte IRQ controller has two different register blocks: a global ARM block mapped at the same address as on the Wii, and a new SMP block for each PPC core to use.
+The Latte IRQ engine has two different register blocks: a global block compatible with the old Wii hardware (Wood), and a new SMP block split across the three Wii U's (Latte) PPC cores and the ARM core. Each core's region of the SMP block has registers equivalent to the old global block.
−===Global ARM block===
+{{reglist|Global ARM block}}
+===Compat block===
−{{rla|0x0d800030|32|LT_INTSR_PPC|Triggered IRQs for the PPC}}
+{{reglist|Global compat block}}
−{{rla|0x0d800034|32|LT_INTMR_PPC|Allowed IRQs for the PPC}}
+{{rla|0x0d800030|32|LT_INTSR_PPC_COMPAT|Triggered IRQs for the PPC in vWii}}
−{{rla|0x0d800038|32|LT_INTSR_ARM|Triggered IRQs for the ARM}}
+{{rla|0x0d800034|32|LT_INTMR_PPC_COMPAT|Allowed IRQs for the PPC in vWii}}
−{{rla|0x0d80003c|32|LT_INTMR_ARM|Allowed IRQs for the ARM}}
+{{rla|0x0d800038|32|LT_INTSR_ARM_COMPAT|Triggered IRQs for the ARM in vWii}}
+{{rla|0x0d80003c|32|LT_INTMR_ARM_COMPAT|Allowed IRQs for the ARM in vWii}}
+{{rld|0x0d800040|32|LT_INTMR_ARM2x_COMPAT|Unknown}}
|}
|}
===SMP block===
===SMP block===
{{reglist|SMP block - PPC core 0}}
{{reglist|SMP block - PPC core 0}}
−{{rla|0x0d800440|32|LT_INTSR_AHBALL_PPC0|Triggered AHB (all) IRQs for PPC core 0}}
+{{rla|0x0d800440|32|LT_INTSR_AHBALL_PPC0|Triggered AHB IRQs for PPC core 0 (all)}}
−{{rla|0x0d800444|32|LT_INTSR_AHBLT_PPC0|Triggered AHB (Latte) IRQs for PPC core 0}}
+{{rla|0x0d800444|32|LT_INTSR_AHBLT_PPC0|Triggered AHB IRQs for PPC core 0 (Latte only)}}
−{{rla|0x0d800448|32|LT_INTMR_AHBALL_PPC0|Allowed AHB (all) IRQs for PPC core 0}}
+{{rla|0x0d800448|32|LT_INTMR_AHBALL_PPC0|Allowed AHB IRQs for PPC core 0 (all)}}
−{{rla|0x0d80044c|32|LT_INTMR_AHBLT_PPC0|Allowed AHB (Latte) IRQs for PPC core 0}}
+{{rla|0x0d80044c|32|LT_INTMR_AHBLT_PPC0|Allowed AHB IRQs for PPC core 0 (Latte only)}}
|}
|}
{{reglist|SMP block - PPC core 1}}
{{reglist|SMP block - PPC core 1}}
−{{rla|0x0d800450|32|LT_INTSR_AHBALL_PPC1|Triggered AHB (all) IRQs for PPC core 1}}
+{{rla|0x0d800450|32|LT_INTSR_AHBALL_PPC1|Triggered AHB IRQs for PPC core 1 (all)}}
−{{rla|0x0d800454|32|LT_INTSR_AHBLT_PPC1|Triggered AHB (Latte) IRQs for PPC core 1}}
+{{rla|0x0d800454|32|LT_INTSR_AHBLT_PPC1|Triggered AHB IRQs for PPC core 1 (Latte only)}}
−{{rla|0x0d800458|32|LT_INTMR_AHBALL_PPC1|Allowed AHB (all) IRQs for PPC core 1}}
+{{rla|0x0d800458|32|LT_INTMR_AHBALL_PPC1|Allowed AHB IRQs for PPC core 1 (all)}}
−{{rla|0x0d80045c|32|LT_INTMR_AHBLT_PPC1|Allowed AHB (Latte) IRQs for PPC core 1}}
+{{rla|0x0d80045c|32|LT_INTMR_AHBLT_PPC1|Allowed AHB IRQs for PPC core 1 (Latte only)}}
|}
|}
{{reglist|SMP block - PPC core 2}}
{{reglist|SMP block - PPC core 2}}
−{{rla|0x0d800460|32|LT_INTSR_AHBALL_PPC2|Triggered AHB (all) IRQs for PPC core 2}}
+{{rla|0x0d800460|32|LT_INTSR_AHBALL_PPC2|Triggered AHB IRQs for PPC core 2 (all)}}
−{{rla|0x0d800464|32|LT_INTSR_AHBLT_PPC2|Triggered AHB (Latte) IRQs for PPC core 2}}
+{{rla|0x0d800464|32|LT_INTSR_AHBLT_PPC2|Triggered AHB IRQs for PPC core 2 (Latte only)}}
−{{rla|0x0d800468|32|LT_INTMR_AHBALL_PPC2|Allowed AHB (all) IRQs for PPC core 2}}
+{{rla|0x0d800468|32|LT_INTMR_AHBALL_PPC2|Allowed AHB IRQs for PPC core 2 (all)}}
−{{rla|0x0d80046c|32|LT_INTMR_AHBLT_PPC2|Allowed AHB (Latte) IRQs for PPC core 2}}
+{{rla|0x0d80046c|32|LT_INTMR_AHBLT_PPC2|Allowed AHB IRQs for PPC core 2 (Latte only)}}
+|}
+{{reglist|SMP block - ARM core}}
+{{rla|0x0d800470|32|LT_INTSR_AHBALL_ARM|Triggered AHB IRQs for ARM core (all)}}
+{{rla|0x0d800474|32|LT_INTSR_AHBLT_ARM|Triggered AHB IRQs for ARM core (Latte only)}}
+{{rla|0x0d800478|32|LT_INTMR_AHBALL_ARM|Allowed AHB IRQs for ARM core (all)}}
+{{rla|0x0d80047c|32|LT_INTMR_AHBLT_ARM|Allowed AHB IRQs for ARM core (Latte only)}}
+{{rld|0x0d800480|32|LT_INTMR_AHBALL_ARM2x|Unknown (all)}}
+{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x|Unknown (Latte only)}}
|}
|}