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Hardware/Latte registers (view source)
Revision as of 00:09, 27 November 2023
, 00:09, 27 November 2023Better names for several registers
Line 29:
Line 29:
{{rld|0x0d800040|32|HW_IOPFIQINTEN}}
{{rld|0x0d800040|32|HW_IOPFIQINTEN}}
{{rld|0x0d800044|32|HW_IOPINTPPC|Unknown}}
{{rld|0x0d800044|32|HW_IOPINTPPC|Unknown}}
−{{rld|0x0d800048|32|HW_WDGINTSTS|AHB Watchdog interrupt status}}
+{{rld|0x0d800048|32|HW_WDGINTSTS|Watchdog interrupt status}}
−{{rld|0x0d80004c|32|HW_WDGCFG|AHB Watchdog configuration}}
+{{rld|0x0d80004c|32|HW_WDGCFG|Watchdog configuration}}
−{{rld|0x0d800050|32|HW_DMAADRINTSTS|AHB DMA transfer interrupt status}}
+{{rld|0x0d800050|32|HW_DMAADRINTSTS|DMA transfer interrupt status}}
−{{rld|0x0d800054|32|HW_CPUADRINTSTS|AHB CPU transfer interrupt status}}
+{{rld|0x0d800054|32|HW_CPUADRINTSTS|CPU transfer interrupt status}}
{{rld|0x0d800058|32|HW_DBGINTSTS|Debug interrupt status}}
{{rld|0x0d800058|32|HW_DBGINTSTS|Debug interrupt status}}
{{rld|0x0d80005c|32|HW_DBGINTEN|Debug interrupt enable}}
{{rld|0x0d80005c|32|HW_DBGINTEN|Debug interrupt enable}}
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
−{{rld|0x0d800068|32|HW_I2CIOPINTEN|[[Hardware/Latte I²C|IOP I²C]] (used for the AV encoder)|drs=2}}
+{{rld|0x0d800068|32|HW_I2CIOPINTEN|I2C interrupt enable}}
−{{rld|0x0d80006c|32|HW_I2CIOPINTSTS}}
+{{rld|0x0d80006c|32|HW_I2CIOPINTSTS|I2C interrupt status}}
{{rld|0x0d800070|32|HW_AIPPROT|[[Hardware/Legacy#External_Interface|EXI]] access control}}
{{rld|0x0d800070|32|HW_AIPPROT|[[Hardware/Legacy#External_Interface|EXI]] access control}}
{{rld|0x0d800074|32|HW_AIPIOCTRL|Unknown}}
{{rld|0x0d800074|32|HW_AIPIOCTRL|Unknown}}
−{{rld|0x0d800078|32|HW_VIINTEN|Unknown}}
+{{rld|0x0d800078|32|HW_VIINTEN|VI interrupt enable}}
−{{rld|0x0d80007c|32|HW_VIINTSTS|Unknown}}
+{{rld|0x0d80007c|32|HW_VIINTSTS|VI interrupt status}}
{{rld|0x0d800080|32|HW_USBDBG0|USB related|drs=4}}
{{rld|0x0d800080|32|HW_USBDBG0|USB related|drs=4}}
{{rld|0x0d800084|32|HW_USBDBG1}}
{{rld|0x0d800084|32|HW_USBDBG1}}
{{rld|0x0d800088|32|HW_USBFRCRST}}
{{rld|0x0d800088|32|HW_USBFRCRST}}
{{rld|0x0d80008c|32|HW_USBIOTEST}}
{{rld|0x0d80008c|32|HW_USBIOTEST}}
−{{rld|0x0d800090|32|HW_ELA_REG_ADDR|CoreSight ELA|drs=4}}
+{{rld|0x0d800090|32|HW_ELAREGADDR|CoreSight ELA|drs=4}}
−{{rld|0x0d800094|32|HW_ELA_REG_DATA}}
+{{rld|0x0d800094|32|HW_ELAREGDATA}}
{{rld|0x0d800098|32|HW_MEMTSTN}}
{{rld|0x0d800098|32|HW_MEMTSTN}}
{{rld|0x0d80009c|32|HW_MEMTSTP}}
{{rld|0x0d80009c|32|HW_MEMTSTP}}
Line 67:
Line 67:
{{rld|0x0d8000f8|32|HW_GPIOIOPSTRAPS}}
{{rld|0x0d8000f8|32|HW_GPIOIOPSTRAPS}}
{{rld|0x0d8000fc|32|HW_GPIOIOPPPCOWNER}}
{{rld|0x0d8000fc|32|HW_GPIOIOPPPCOWNER}}
−{{rld|0x0d800100|32|HW_ARB_CFG_M0|AHB arbiter configuration|drs=20}}
+{{rld|0x0d800100|32|HW_ARBCFGM0|AHB arbiter configuration|drs=20}}
−{{rld|0x0d800104|32|HW_ARB_CFG_M1}}
+{{rld|0x0d800104|32|HW_ARBCFGM1}}
−{{rld|0x0d800108|32|HW_ARB_CFG_M2}}
+{{rld|0x0d800108|32|HW_ARBCFGM2}}
−{{rld|0x0d80010c|32|HW_ARB_CFG_M3}}
+{{rld|0x0d80010c|32|HW_ARBCFGM3}}
−{{rld|0x0d800110|32|HW_ARB_CFG_M4}}
+{{rld|0x0d800110|32|HW_ARBCFGM4}}
−{{rld|0x0d800114|32|HW_ARB_CFG_M5}}
+{{rld|0x0d800114|32|HW_ARBCFGM5}}
−{{rld|0x0d800118|32|HW_ARB_CFG_M6}}
+{{rld|0x0d800118|32|HW_ARBCFGM6}}
−{{rld|0x0d80011c|32|HW_ARB_CFG_M7}}
+{{rld|0x0d80011c|32|HW_ARBCFGM7}}
−{{rld|0x0d800120|32|HW_ARB_CFG_M8}}
+{{rld|0x0d800120|32|HW_ARBCFGM8}}
−{{rld|0x0d800124|32|HW_ARB_CFG_M9}}
+{{rld|0x0d800124|32|HW_ARBCFGM9}}
−{{rld|0x0d800128|32|HW_ARB_CFG_MA}}
+{{rld|0x0d800128|32|HW_ARBCFGMA}}
−{{rld|0x0d80012c|32|HW_ARB_CFG_MB}}
+{{rld|0x0d80012c|32|HW_ARBCFGMB}}
−{{rld|0x0d800130|32|HW_ARB_CFG_MC}}
+{{rld|0x0d800130|32|HW_ARBCFGMC}}
−{{rld|0x0d800134|32|HW_ARB_CFG_MD}}
+{{rld|0x0d800134|32|HW_ARBCFGMD}}
−{{rld|0x0d800138|32|HW_ARB_CFG_ME}}
+{{rld|0x0d800138|32|HW_ARBCFGME}}
−{{rld|0x0d80013c|32|HW_ARB_CFG_MF}}
+{{rld|0x0d80013c|32|HW_ARBCFGMF}}
−{{rld|0x0d800140|32|HW_ARB_CFG_CPU}}
+{{rld|0x0d800140|32|HW_ARBCFGCPU}}
−{{rld|0x0d800144|32|HW_ARB_CFG_DMA}}
+{{rld|0x0d800144|32|HW_ARBCFGDMA}}
−{{rld|0x0d800148|32|HW_ARB_PCNTCFG}}
+{{rld|0x0d800148|32|HW_ARBPCNTCFG}}
−{{rld|0x0d80014c|32|HW_ARB_PCNTSTS}}
+{{rld|0x0d80014c|32|HW_ARBPCNTSTS}}
−{{rld|0x0d800150|32|HW_I2CSCTRL|Unknown|drs=7}}
+{{rld|0x0d800150|32|HW_I2CSCTRL|[[Hardware/Latte I2C|I2C slave]] (VI)|drs=7}}
{{rld|0x0d800154|32|HW_I2CSSTS}}
{{rld|0x0d800154|32|HW_I2CSSTS}}
{{rld|0x0d800158|32|HW_I2CSRDEN}}
{{rld|0x0d800158|32|HW_I2CSRDEN}}
−{{rld|0x0d800160|32|HW_I2CSTRAP}}
+{{rld|0x0d800160|32|HW_I2CSGAMMA}}
−{{rld|0x0d800164|32|HW_I2CSCTRL}}
+{{rld|0x0d800164|32|HW_I2CSTRAP}}
{{rld|0x0d800168|32|HW_I2CSVISETYUV}}
{{rld|0x0d800168|32|HW_I2CSVISETYUV}}
{{rld|0x0d80016c|32|HW_I2CSVISETFILT}}
{{rld|0x0d80016c|32|HW_I2CSVISETFILT}}
Line 97:
Line 97:
{{rld|0x0d800174|32|HW_SPARE3|Unknown}}
{{rld|0x0d800174|32|HW_SPARE3|Unknown}}
{{rld|0x0d800180|32|HW_COMPAT|Drive interface resets}}
{{rld|0x0d800180|32|HW_COMPAT|Drive interface resets}}
−{{rla|0x0d800184|32|HW_RSTAHB|Memory resets}}
+{{rla|0x0d800184|32|HW_RSTAHB|AHB reset control}}
{{rld|0x0d800188|32|HW_SPARE0|Unknown}}
{{rld|0x0d800188|32|HW_SPARE0|Unknown}}
{{rla|0x0d80018c|32|HW_SPARE1|Maps boot0 and controls a few other things}}
{{rla|0x0d80018c|32|HW_SPARE1|Maps boot0 and controls a few other things}}
Line 128:
Line 128:
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
{{rld|0x0d8001f8|32|HW_OBSCLKOCTRL}}
{{rld|0x0d8001fc|32|HW_OBSCLKICTRL}}
{{rld|0x0d8001fc|32|HW_OBSCLKICTRL}}
−{{rla|0x0d800200|32|LT_DBGPORT}}
+{{rla|0x0d800200|32|HW_DBGPORT}}
{{rld|0x0d800204|32|HW_SICLKDIV|SI related|drs=4}}
{{rld|0x0d800204|32|HW_SICLKDIV|SI related|drs=4}}
{{rld|0x0d800208|32|HW_SICTRL}}
{{rld|0x0d800208|32|HW_SICTRL}}
Line 134:
Line 134:
{{rld|0x0d800210|32|HW_SIINT}}
{{rld|0x0d800210|32|HW_SIINT}}
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
−{{rla|0x0d800218|32|LT_DBGBUSRD|Unknown}}
+{{rla|0x0d800218|32|HW_DBGBUSRD|Debug bus read value}}
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
−{{rld|0x0d800250|32|HW_AVE_I2C_CLOCK{{check}}|[[Hardware/Latte I²C|AV encoder I²C]]|drs=4}}
+{{rld|0x0d800250|32|HW_I2CMCTRL|[[Hardware/Latte I2C|I2C master]] (A/V encoder)|drs=4}}
−{{rld|0x0d800254|32|HW_AVE_I2C_INOUT_DATA}}
+{{rld|0x0d800254|32|HW_I2CMDATAWR}}
−{{rld|0x0d800258|32|HW_AVE_I2C_INOUT_CTRL}}
+{{rld|0x0d800258|32|HW_I2CMWREN}}
−{{rld|0x0d80025c|32|HW_AVE_I2C_INOUT_SIZE}}
+{{rld|0x0d80025c|32|HW_I2CMDATARD}}
{{rld|0x0d800400|32|LT_IPCPPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
{{rld|0x0d800400|32|LT_IPCPPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
{{rld|0x0d800404|32|LT_IPCPPCCTRL0}}
{{rld|0x0d800404|32|LT_IPCPPCCTRL0}}
Line 170:
Line 170:
{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}
{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE}}
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE}}
−{{rld|0x0d8004a0|32|LT_WDG2INTSTS|AHB Watchdog interrupt status}}
+{{rld|0x0d8004a0|32|LT_WDG2INTSTS|Watchdog interrupt status}}
−{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|AHB DMA transfer interrupt status}}
+{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|DMA transfer interrupt status}}
−{{rld|0x0d8004a8|32|LT_CPUADR2INTSTS|AHB CPU transfer interrupt status}}
+{{rld|0x0d8004a8|32|LT_CPUADR2INTSTS|CPU transfer interrupt status}}
−{{rld|0x0d8004c8|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004c0|32|LT_ARBCFGM0|AHB arbiter configuration|drs=10}}
−{{rld|0x0d8004cc|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004c4|32|LT_ARBCFGM1}}
−{{rld|0x0d8004d0|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004c8|32|LT_ARBCFGM2}}
−{{rld|0x0d8004d4|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004cc|32|LT_ARBCFGM3}}
−{{rld|0x0d8004dc|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004d0|32|LT_ARBCFGM4}}
−{{rld|0x0d8004e0|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004d4|32|LT_ARBCFGM5}}
−{{rld|0x0d8004e4|32|UNKNOWN|Unknown}}
+{{rld|0x0d8004d8|32|LT_ARBCFGM6}}
+{{rld|0x0d8004dc|32|LT_ARBCFGM7}}
+{{rld|0x0d8004e0|32|LT_ARBCFGM8}}
+{{rld|0x0d8004e4|32|LT_ARBCFGM9}}
{{rld|0x0d800500|32|LT_PPCBUSPROT|AHB access control for the PPC}}
{{rld|0x0d800500|32|LT_PPCBUSPROT|AHB access control for the PPC}}
{{rld|0x0d800504|32|LT_IOPBUSPROT|AHB access control for the IOP}}
{{rld|0x0d800504|32|LT_IOPBUSPROT|AHB access control for the IOP}}
−{{rla|0x0d800510|32|LT_EFUSEPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each)}}
+{{rla|0x0d800510|32|LT_EFUSEPROT|OTP access control}}
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for Wood}}
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for Wood}}
{{rld|0x0d800520|32|LT_GPIOPPCOUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
{{rld|0x0d800520|32|LT_GPIOPPCOUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
Line 200:
Line 203:
{{rld|0x0d800558|32|LT_GPIOIOPSTRAPS}}
{{rld|0x0d800558|32|LT_GPIOIOPSTRAPS}}
{{rld|0x0d80055c|32|LT_GPIOIOPPPCOWNER}}
{{rld|0x0d80055c|32|LT_GPIOIOPPPCOWNER}}
−{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK|[[Hardware/Latte I²C|SMC I²C]]|drs=6}}
+{{rld|0x0d800570|32|LT_I2CMCTRL|[[Hardware/Latte I2C|I2C master]] (SMC)|drs=4}}
−{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
+{{rld|0x0d800574|32|LT_I2CMDATAWR}}
−{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
+{{rld|0x0d800578|32|LT_I2CMWREN}}
−{{rld|0x0d80057c|32|LT_SMC_I2C_INOUT_SIZE}}
+{{rld|0x0d80057c|32|LT_I2CMDATARD}}
−{{rld|0x0d800580|32|LT_SMC_I2C_INT_MASK}}
+{{rld|0x0d800580|32|LT_I2CIOPINTEN|I2C interrupt status}}
−{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
+{{rld|0x0d800584|32|LT_I2CIOPINTSTS|I2C interrupt enable}}
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
{{rla|0x0d8005a4|32|LT_SYSCFG1|System configuration}}
{{rla|0x0d8005a4|32|LT_SYSCFG1|System configuration}}
−{{rla|0x0d8005b0|32|LT_MEMCMPT|Memory compat mode for Wood}}
+{{rla|0x0d8005b0|32|LT_PIMEMCOMPAT|Processor interface memory bus compat mode for Wood}}
−{{rld|0x0d8005b4|32|LT_AHBCMPT|AHB compat mode for Wood}}
+{{rld|0x0d8005b4|32|LT_AHBCOMPAT|AHB compat mode for Wood}}
−{{rld|0x0d8005b8|32|LT_AICMPT|AI compat mode for Wood}}
+{{rld|0x0d8005b8|32|LT_AICOMPAT|AI compat mode for Wood}}
−{{rld|0x0d8005bc|32|LT_IOP2X|Toggles the IOP clock multiplier}}
+{{rld|0x0d8005bc|32|LT_IOP2XCTRL|IOP clock multiplier control}}
−{{rld|0x0d8005c0|32|LT_EXICMPT|EXI compat mode for Wood}}
+{{rld|0x0d8005c0|32|LT_EXICOMPAT|EXI compat mode for Wood}}
−{{rld|0x0d8005c8|32|LT_IOSTRCTRL|I/O power strength control}}
+{{rld|0x0d8005c4|32|LT_IOPWRCTRL|I/O power control}}
−{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
+{{rld|0x0d8005c8|32|LT_IOSTRCTRL0|I/O power strength control}}
−{{rla|0x0d8005e0|32|LT_RSTCTRL0|Reset control}}
+{{rld|0x0d8005cc|32|LT_IOSTRCTRL1|I/O power strength control}}
−{{rla|0x0d8005e4|32|LT_RSTCTRL1|Reset control}}
+{{rla|0x0d8005e0|32|LT_RSTCTRL|Reset control}}
+{{rla|0x0d8005e4|32|LT_RSTAHB|AHB reset control}}
{{rld|0x0d8005e8|32|LT_CLKGATE|Clock gating}}
{{rld|0x0d8005e8|32|LT_CLKGATE|Clock gating}}
−{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
+{{rld|0x0d8005ec|32|LT_CLKCTRL|Clock control}}
−{{rla|0x0d800620|32|LT_ABIF_ADDR|ASIC bus interface|drs=2}}
+{{rla|0x0d800620|32|LT_ABIFADDR|ASIC bus interface|drs=2}}
−{{rld|0x0d800624|32|LT_ABIF_DATA}}
+{{rld|0x0d800624|32|LT_ABIFDATA}}
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
−{{rld|0x0d800640|32|LT_60XE_CFG|60Xe data bus configuration}}
+{{rld|0x0d800640|32|LT_PIMEMCFG|Processor interface memory bus configuration}}
−{{rld|0x0d800660|32|UNKNOWN|Unknown}}
+{{rld|0x0d800660|32|LT_SATACFG|SATA configuration}}
{{rld|0x0d800664|32|UNKNOWN|Unknown}}
{{rld|0x0d800664|32|UNKNOWN|Unknown}}
{{rld|0x0d800668|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
{{rld|0x0d800668|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
Line 229:
Line 233:
{{rld|0x0d800670|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
{{rld|0x0d800670|32|UNKNOWN|Unknown (bitmask 0x0FFFFFFF)}}
{{rld|0x0d80067c|32|UNKNOWN|Unknown (bitmask 0x3f00ff00)}}
{{rld|0x0d80067c|32|UNKNOWN|Unknown (bitmask 0x3f00ff00)}}
−{{rld|0x0d8006a0|32|LT_DMCU_WRITE|[[Hardware/DMCU|DMCU]] write value (bitmask 0x0FFFFFFF)}}
+{{rld|0x0d8006a0|32|LT_DMCUDATAWR|[[Hardware/DMCU|DMCU]] data write (bitmask 0x0FFFFFFF)}}
−{{rld|0x0d8006a8|32|LT_DMCU_CONTROL|[[Hardware/DMCU|DMCU]] control register (bitmask 0x80000001)}}
+{{rld|0x0d8006a4|32|LT_DMCUDATARD|[[Hardware/DMCU|DMCU]] data read (bitmask 0x0FFFFFFF)}}
−{{rld|0x0d800700|32|UNKNOWN|Unknown (bitmask 0x7FFFFFFF)}}
+{{rld|0x0d8006a8|32|LT_DMCUCTRL|[[Hardware/DMCU|DMCU]] control register (bitmask 0x80000001)}}
−{{rld|0x0d800704|32|UNKNOWN|Unknown (bitmask 0x7F7FFFFF)}}
+{{rld|0x0d800700|32|LT_SPARE0|Unknown (bitmask 0x7FFFFFFF)}}
−{{rld|0x0d800708|32|LT_DCCMPT|DC compat mode for Wood (bitmask 0x7FFFFFFF)}}
+{{rld|0x0d800704|32|LT_SPARE1|Unknown (bitmask 0x7F7FFFFF)}}
−{{rld|0x0d80070c|32|UNKNOWN|Unknown (bitmask 0x7FFFFFFF)}}
+{{rld|0x0d800708|32|LT_SPARE2|DC compat mode for Wood (bitmask 0x7FFFFFFF)}}
+{{rld|0x0d80070c|32|LT_SPARE3|Unknown (bitmask 0x7FFFFFFF)}}
|}
|}
Line 337:
Line 342:
}}
}}
−{{reg32 | LT_DBGPORT | addr = 0x0d800200 | hifields = 2 | lofields = 3 |
+{{reg32 | HW_DBGPORT | addr = 0x0d800200 | hifields = 2 | lofields = 3 |
|5 |11 |
|5 |11 |
|? |R/W |
|? |R/W |
Line 345:
Line 350:
|DBGPORT_BIT15 | |GPIO_EN|
|DBGPORT_BIT15 | |GPIO_EN|
}}
}}
−This seems to select internal debug values to be viewed in LT_DBGBUSRD, as well as [[Hardware/Latte_GPIOs|external GPIOs]] if GPIO_EN is set. Values are split by u16s.
+This seems to select internal debug values to be viewed in HW_DBGBUSRD, as well as [[Hardware/Latte_GPIOs|external GPIOs]] if GPIO_EN is set. Values are split by u16s.
{{regdesc
{{regdesc
−|DBG_ID|Selects the values outputted to the low and high LT_DBGBUSRD u16s.
+|DBG_ID|Selects the values outputted to the low and high HW_DBGBUSRD u16s.
−|DBGPORT_BIT15|Mirrors the upper u16 in LT_DBGBUSRD to the lower u16.
+|DBGPORT_BIT15|Mirrors the upper u16 in HW_DBGBUSRD to the lower u16.
−|GPIO_EN|Outputs {LT_DBGBUSRD[11:8], LT_DBGBUSRD[15:12]} to [[Hardware/Latte_GPIOs|NDEV_LED]] (and other GPIOs?)
+|GPIO_EN|Outputs {HW_DBGBUSRD[11:8], HW_DBGBUSRD[15:12]} to [[Hardware/Latte_GPIOs|NDEV_LED]] (and other GPIOs?)
}}
}}
Line 535:
Line 540:
}}
}}
−{{reg32 | LT_MEMCMPT | addr = 0x0d8005b0 | hifields = 1 | lofields = 3 |
+{{reg32 | LT_PIMEMCOMPAT | addr = 0x0d8005b0 | hifields = 1 | lofields = 3 |
|16 |
|16 |
|? |
|? |
Line 547:
Line 552:
}}
}}
−{{reg32 | LT_RSTCTRL0 | addr = 0x0d8005e0 | hifields = 1 | lofields = 3 |
+{{reg32 | LT_RSTCTRL | addr = 0x0d8005e0 | hifields = 1 | lofields = 3 |
|16 |
|16 |
|? |
|? |
Line 559:
Line 564:
}}
}}
−{{reg32 | LT_RSTCTRL1 | addr = 0x0d8005e4 | hifields = 1 | lofields = 5 |
+{{reg32 | LT_RSTAHB | addr = 0x0d8005e4 | hifields = 1 | lofields = 5 |
|16 |
|16 |
|? |
|? |
Line 572:
Line 577:
}}
}}
−{{reg32 | LT_ABIF_ADDR | addr = 0x0d800620 | hifields = 3 | lofields = 1 |
+{{reg32 | LT_ABIFADDR | addr = 0x0d800620 | hifields = 3 | lofields = 1 |
|2 |6 |8 |
|2 |6 |8 |
|R/W |R/W |R/W |
|R/W |R/W |R/W |
Line 584:
Line 589:
|tile_id|See below
|tile_id|See below
|device |See below
|device |See below
−|offset |Offset into registers, acccessed through LT_ABIF_DATA.
+|offset |Offset into registers, acccessed through LT_ABIFDATA.
}}
}}
'''tile_id'''/'''device''' values:
'''tile_id'''/'''device''' values: