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Hardware/Latte registers

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Revision as of 23:34, 25 January 2016 by Hykem (talk | contribs)

The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the Espresso. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.

Latte registers
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800000
Length0x800[check]
Access size32 bits
Byte orderBig Endian
IRQs
Espresso12
Latte0,10,11,17,30,31,...[check]
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Register list

Latte Registers
Address Bits Name Description
0x0d800000 32 LT_IPC_PPCMSG IPC
0x0d800004 32 LT_IPC_PPCCTRL
0x0d800008 32 LT_IPC_ARMMSG
0x0d80000c 32 LT_IPC_ARMCTRL
0x0d800010 32 LT_TIMER Starbuck Timer
0x0d800014 32 LT_ALARM
0x0d800030 32 LT_INTSR_PPC Latte IRQs
0x0d800034 32 LT_INTMR_PPC
0x0d800038 32 LT_INTSR_ARM
0x0d80003c 32 LT_INTMR_ARM
0x0d800040 32 UNKNOWN Unknown
0x0d80004c 32 UNKNOWN Unknown
0x0d800050 32 LT_SYSPROTDRV_UNK1 System protection driver
0x0d800054 32 LT_SYSPROTDRV_UNK2
0x0d800058 32 LT_SYSPROTDRV_UNK3
0x0d80005c 32 LT_SYSPROTDRV_UNK4
0x0d800060 32 LT_MEMIRR Memory control[check]
0x0d800064 32 LT_AHBPROT Access control for the PPC to access devices on the AHB
0x0d800068 32 UNKNOWN Unknown
0x0d80006c 32 UNKNOWN Unknown
0x0d800070 32 LT_EXICTRL EXI PPC enable / control / other [check]
0x0d800074 32 UNKNOWN Unknown
0x0d800088 32 UNKNOWN DDR?
0x0d8000c0 32 LT_GPIOE_OUT Latte GPIOs
0x0d8000c4 32 LT_GPIOE_DIR
0x0d8000c8 32 LT_GPIOE_IN
0x0d8000cc 32 LT_GPIOE_INTLVL
0x0d8000d0 32 LT_GPIOE_INTFLAG
0x0d8000d4 32 LT_GPIOE_INTMASK
0x0d8000d8 32 LT_GPIOE_INMIR
0x0d8000dc 32 LT_GPIO_ENABLE
0x0d8000e0 32 LT_GPIO_OUT
0x0d8000e4 32 LT_GPIO_DIR
0x0d8000e8 32 LT_GPIO_IN
0x0d8000ec 32 LT_GPIO_INTLVL
0x0d8000f0 32 LT_GPIO_INTFLAG
0x0d8000f4 32 LT_GPIO_INTMASK
0x0d8000f8 32 LT_GPIO_INMIR
0x0d8000fc 32 LT_GPIO_OWNER
0x0d800100 32 LT_AHB_UNK1 AHB specific registers
0x0d800104 32 LT_AHB_UNK2
0x0d800108 32 LT_AHB_UNK3
0x0d80010c 32 LT_AHB_UNK4
0x0d800110 32 LT_AHB_UNK5
0x0d800114 32 LT_AHB_UNK6
0x0d800118 32 LT_AHB_UNK7
0x0d80011c 32 LT_AHB_UNK8
0x0d800120 32 LT_AHB_UNK9
0x0d800124 32 LT_AHB_UNK10
0x0d800130 32 LT_AHB_UNK11
0x0d800134 32 LT_AHB_UNK12
0x0d800138 32 LT_AHB_UNK13
0x0d800140 32 LT_WORKAROUNDS Unknown
0x0d800180 32 LT_DIFLAGS Drive interface stuff[check]
0x0d800184 32 LT_UNKFLAGS Unknown flags
0x0d800188 32 UNKNOWN Unknown
0x0d80018c 32 LT_BOOT0 Maps boot0 [check]
0x0d800190 32 LT_CLOCKINFO Clock information
0x0d800194 32 LT_RESETS System resets [check]
0x0d800198 32 LT_CLOCKGATE Interfaces' clock gate
0x0d8001a8 32 LT_SATAPLL_UNK1 Unknown
0x0d8001c8 32 LT_SATAPLL_UNK2 Unknown
0x0d8001cc 32 LT_SATAPLL_UNK3 Unknown
0x0d8001d0 32 LT_SATAPLL_UNK4 Unknown
0x0d8001d8 32 UNKNOWN Unknown
0x0d8001dc 32 LT_IOPOWER Subsystems' power state
0x0d8001e0 32 LT_IOSTRENGTH1 Subsystems' power strength
0x0d8001e4 32 LT_IOSTRENGTH2 Subsystems' power strength
0x0d8001e8 32 UNKNOWN Unknown
0x0d8001ec 32 LT_OTPCMD OTP
0x0d8001f0 32 LT_OTPDATA
0x0d800204 32 UNKNOWN Unknown
0x0d800214 32 LT_VERSION Latte version
0x0d800250 32 UNKNOWN Unknown
0x0d800254 32 UNKNOWN Unknown
0x0d800258 32 UNKNOWN Unknown
0x0d800400 32 LT_IPC_PPC0_PPCMSG IPC (per-core)
0x0d800404 32 LT_IPC_PPC0_PPCCTRL
0x0d800408 32 LT_IPC_PPC0_ARMMSG
0x0d80040c 32 LT_IPC_PPC0_ARMCTRL
0x0d800410 32 LT_IPC_PPC1_PPCMSG
0x0d800414 32 LT_IPC_PPC1_PPCCTRL
0x0d800418 32 LT_IPC_PPC1_ARMMSG
0x0d80041c 32 LT_IPC_PPC1_ARMCTRL
0x0d800420 32 LT_IPC_PPC2_PPCMSG
0x0d800424 32 LT_IPC_PPC2_PPCCTRL
0x0d800428 32 LT_IPC_PPC2_ARMMSG
0x0d80042c 32 LT_IPC_PPC2_ARMCTRL
0x0d800440 32 LT_INTSR_AHBALL_PPC0 Latte IRQs (per-core)
0x0d800444 32 LT_INTSR_AHBLT_PPC0
0x0d800448 32 LT_INTMR_AHBALL_PPC0
0x0d80044c 32 LT_INTMR_AHBLT_PPC0
0x0d800450 32 LT_INTSR_AHBALL_PPC1
0x0d800454 32 LT_INTSR_AHBLT_PPC1
0x0d800458 32 LT_INTMR_AHBALL_PPC1
0x0d80045c 32 LT_INTMR_AHBLT_PPC1
0x0d800460 32 LT_INTSR_AHBALL_PPC2
0x0d800464 32 LT_INTSR_AHBLT_PPC2
0x0d800468 32 LT_INTMR_AHBALL_PPC2
0x0d80046c 32 LT_INTMR_AHBLT_PPC2
0x0d800470 32 LT_INTSR_ARM2 Unknown duplicate
0x0d800474 32 LT_GPIO_INTFLAG2 Unknown duplicate
0x0d800478 32 LT_INTMR_ARM2 Unknown duplicate
0x0d80047c 32 LT_GPIO_INTMASK2 Unknown duplicate
0x0d800480 32 UNKNOWN Unknown
0x0d800484 32 UNKNOWN Unknown
0x0d8004a4 32 LT_SYSPROTDRV_UNK5 System protection driver (mirror?)
0x0d8004a8 32 LT_SYSPROTDRV_UNK6
0x0d800500 32 UNKNOWN Unknown
0x0d800504 32 UNKNOWN Unknown
0x0d800510 32 LT_OTPPROT Bitmask used to lock out chunks of OTP (0x20 bytes each).
0x0d800514 32 LT_SYSPROT Hardware sandbox for vWii mode
0x0d800520 32 LT_GPIOE_OUT2 Latte GPIOs (mirror?)
0x0d800524 32 LT_GPIOE_DIR2
0x0d800528 32 LT_GPIOE_IN2
0x0d80052c 32 LT_GPIOE_INTLVL2
0x0d800530 32 LT_GPIOE_INTFLAG2
0x0d800534 32 LT_GPIOE_INTMASK2
0x0d800538 32 LT_GPIOE_INMIR2
0x0d80053c 32 LT_GPIO_ENABLE2
0x0d800540 32 LT_GPIO_OUT2
0x0d800544 32 LT_GPIO_DIR2
0x0d800548 32 LT_GPIO_IN2
0x0d80054c 32 LT_GPIO_INTLVL2
0x0d800550 32 LT_GPIO_INTFLAG2
0x0d800554 32 LT_GPIO_INTMASK2
0x0d800558 32 LT_GPIO_INMIR2
0x0d80055c 32 LT_GPIO_OWNER2
0x0d800570 32 UNKNOWN Unknown
0x0d800574 32 UNKNOWN Unknown
0x0d800578 32 UNKNOWN Unknown
0x0d80057c 32 UNKNOWN Unknown
0x0d800580 32 UNKNOWN Unknown
0x0d800584 32 UNKNOWN Unknown
0x0d8005a0 32 LT_ASICREV ASIC revision
0x0d8005a4 32 LT_DEBUG DEBUG mode flags
0x0d8005b0 32 UNKNOWN Unknown
0x0d8005b8 32 LT_STEREO_OUT_SELECT Stereo mode selector
0x0d8005bc 32 LT_IOP2X Unknown
0x0d8005c8 32 LT_MISC Unknown
0x0d8005cc 32 UNKNOWN Unknown
0x0d8005e4 32 LT_SATASUBSYS Related to the SATA subsystem
0x0d8005e0 32 LT_RESETS2 System resets (mirror)
0x0d8005ec 32 LT_SYSPLL_UNK1 Unknown
0x0d800620 32 LT_SYSPLL_UNK2 Unknown
0x0d800624 32 LT_SYSPLL_UNK3 Unknown
0x0d800628 32 UNKNOWN Unknown
0x0d800640 32 LT_60XE_DATA_STREAMING Unknown
0x0d800660 32 UNKNOWN Unknown
0x0d800640 32 UNKNOWN Unknown
0x0d800708 32 LT_DCCMPT Switch DC video mode (normal/compat)
0x0d8b4226 16 MEM_UNK1 Unknown
0x0d8b4228 16 MEM_FLUSHREQ AHB flush request
0x0d8b422a 16 MEM_FLUSHACK AHB flush ack
0x0d8b42c4 16 MEM_UNK2 Unknown
0x0d8b42c6 16 MEM_UNK3 Unknown
0x0d8b4300 16 MEM_UNK4 Unknown
0x0d8b4302 16 MEM_UNK5 Unknown

General Registers

HW_VERSION (0x0d800214)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access U
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R R
Field VERHI VERLO

This register contains the hardware revision of the Latte chipset. The IOSU also stores this value in a flag inside it's kernel's heap.
Hardware revision -> IOSU equivalent flag
0x00 -> 0x00000001
0x10 -> 0x10000001
0x11 -> 0x10100001 or 0x10100008 or 0x1010000C
0x20 -> 0x20000001
0x21 -> 0x20100001

Field Description
VERHI Version
VERLO Revision


LT_BOOT0 (0x0d80018c)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access ?
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ? R/W R/W ?
Field DSKPLLSRC BOOT0

This register at least controls the boot0 memory mapping and DSK PLL source.

Field Description
BOOT0 Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on LT_MEMMIRR
DSKPLLSRC According to STM, setting this to 00 "puts DSKPLL back to external reference"


LT_DEBUG (0x0d8005a4)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W ?
Field DEBUG
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register at least holds a flag related to DEBUG mode.

Field Description
DEBUG Ask for user input during the IOSU's boot sequence


LT_RESETS2 (0x0d8005e0)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access ?
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register seems to be a mirror of LT_RESETS.


LT_OTPPROT (0x0d800510)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W ?
Field BOOT1
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register is a bitmask for locking out chunks of the OTP.

Field Description
BOOT1 Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7


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