Hardware/Memory controller

The Latte hardware implements AMBA (possibly rev 2.0) compliant AHB buses for communication to/from the Starbuck's CPU and assorted on-chip hardware blocks (DMA, for example).
One of such blocks appears to be a customized memory controller that is responsible for several tasks such as DDR configuration, flushing memory to/from the AHB and employing a custom memory protection solution dubbed MEM_BLOCK.
This controller appears to be an extension of the one that was previously used on the Wii.

Memory controller
Access
Espresso	None
Starbuck	Full
Registers
Base	0x0d8b4000
Length	???
Access size	16 bits
Byte order	Big Endian
IRQs
Espresso	???
Latte	???

Register List

Memory Controller
Address	Bits	Name	Description
0x0d8b4026	16	MEM_UNK	Unknown
0x0d8b4200	16	MEM_COMPAT	Unknown
0x0d8b4202	16	MEM_PROT_REG	Unknown
0x0d8b4204	16	MEM_PROT_SPL	SPL protection enable/disable
0x0d8b4206	16	MEM_PROT_SPL_BASE	SPL protection base address
0x0d8b4208	16	MEM_PROT_SPL_END	SPL protection end address
0x0d8b420a	16	MEM_PROT_DDR	DDR protection enable/disable
0x0d8b420c	16	MEM_PROT_DDR_BASE	DDR protection base address
0x0d8b420e	16	MEM_PROT_DDR_END	DDR protection end address
0x0d8b4210	16	MEM_COLSEL	Unknown
0x0d8b4212	16	MEM_ROWSEL	Unknown
0x0d8b4214	16	MEM_BANKSEL	Unknown
0x0d8b4216	16	MEM_RANKSEL	Unknown
0x0d8b4218	16	MEM_COLMSK	Unknown
0x0d8b421a	16	MEM_ROWMSK	Unknown
0x0d8b421c	16	MEM_BANKMSK	Unknown
0x0d8b421e	16	MEM_PROT_SPL_ERR	SPL protection error
0x0d8b4220	16	MEM_PROT_DDR_ERR	DDR protection error
0x0d8b4222	16	MEM_PROT_SPL_MSK	SPL protection mask
0x0d8b4224	16	MEM_PROT_DDR_MSK	DDR protection mask
0x0d8b4226	16	MEM_RFSH	Unknown
0x0d8b4228	16	MEM_AHMFLUSH	AHB flush request
0x0d8b422a	16	MEM_AHMFLUSH_ACK	AHB flush request acknowledgment
0x0d8b4268	16	MEM_SEQRD_HWM	Unknown
0x0d8b426a	16	MEM_SEQWR_HWM	Unknown
0x0d8b426c	16	MEM_SEQCMD_HWM	Unknown
0x0d8b426e	16	MEM_CPUAHM_WR_T	Unknown
0x0d8b4270	16	MEM_DMAAHM_WR_T	Unknown
0x0d8b4272	16	MEM_DMAAHM0_WR_T	Unknown
0x0d8b4274	16	MEM_DMAAHM1_WR_T	Unknown
0x0d8b4276	16	MEM_PI_WR_T	Unknown
0x0d8b4278	16	MEM_PE_WR_T	Unknown
0x0d8b427a	16	MEM_IO_WR_T	Unknown
0x0d8b427c	16	MEM_DSP_WR_T	Unknown
0x0d8b427e	16	MEM_ACC_WR_T	Unknown
0x0d8b4280	16	MEM_ARB_MAXWR	Unknown
0x0d8b4282	16	MEM_ARB_MINRD	Unknown
0x0d8b4284	16	MEM_PROF_CPUAHM	Unknown
0x0d8b4286	16	MEM_PROF_CPUAHM0	Unknown
0x0d8b4288	16	MEM_PROF_DMAAHM	Unknown
0x0d8b428a	16	MEM_PROF_DMAAHM0	Unknown
0x0d8b428c	16	MEM_PROF_DMAAHM1	Unknown
0x0d8b428e	16	MEM_PROF_PI	Unknown
0x0d8b4290	16	MEM_PROF_VI	Unknown
0x0d8b4292	16	MEM_PROF_IO	Unknown
0x0d8b4294	16	MEM_PROF_DSP	Unknown
0x0d8b4296	16	MEM_PROF_TC	Unknown
0x0d8b4298	16	MEM_PROF_CP	Unknown
0x0d8b429a	16	MEM_PROF_ACC	Unknown
0x0d8b429c	16	MEM_RDPR_CPUAHM	Unknown
0x0d8b429e	16	MEM_RDPR_CPUAHM0	Unknown
0x0d8b42a0	16	MEM_RDPR_DMAAHM	Unknown
0x0d8b42a2	16	MEM_RDPR_DMAAHM0	Unknown
0x0d8b42a4	16	MEM_RDPR_DMAAHM1	Unknown
0x0d8b42a6	16	MEM_RDPR_PI	Unknown
0x0d8b42a8	16	MEM_RDPR_VI	Unknown
0x0d8b42aa	16	MEM_RDPR_IO	Unknown
0x0d8b42ac	16	MEM_RDPR_DSP	Unknown
0x0d8b42ae	16	MEM_RDPR_TC	Unknown
0x0d8b42b0	16	MEM_RDPR_CP	Unknown
0x0d8b42b2	16	MEM_RDPR_ACC	Unknown
0x0d8b42b4	16	MEM_ARB_MAXRD	Unknown
0x0d8b42b6	16	MEM_ARB_MISC	Unknown
0x0d8b42b8	16	MEM_ARAM_EMUL	Unknown
0x0d8b42ba	16	MEM_WRMUX	Unknown
0x0d8b42bc	16	MEM_PERF	Unknown
0x0d8b42be	16	MEM_PERF_READ	Unknown
0x0d8b42c0	16	MEM_ARB_EXADDR	Unknown
0x0d8b42c2	16	MEM_ARB_EXCMD	Unknown
0x0d8b42c4	16	MEM_SEQ_DATA	DDR SEQ register's value to read/write
0x0d8b42c6	16	MEM_SEQ_ADDR	DDR SEQ register's address to read/write
0x0d8b42c8	16	MEM_BIST_DATA	DDR BIST register's address to read/write
0x0d8b42ca	16	MEM_BIST_ADDR	DDR BIST register's address to read/write
0x0d8b42cc	16	MEM_EDRAM_REFRESH_CTRL	EDRAM refresh settings
0x0d8b42ce	16	MEM_EDRAM_REFRESH_VAL	EDRAM refresh value
0x0d8b42d4	16	MEM_MEM1_COMPAT_MODE	Unknown
0x0d8b42d8	16	MEM_UNK	Unknown
0x0d8b4300	16	MEM_SEQ0_DATA	DDR SEQ0 sequential register's value to read/write
0x0d8b4302	16	MEM_SEQ0_ADDR	DDR SEQ0 sequential register's address to read/write
0x0d8b4400	16	MEM_BLOCK_MEM0_CFG	MEM block protection configuration for MEM0
0x0d8b4402	16	MEM_BLOCK_MEM1_CFG	MEM block protection configuration for MEM1
0x0d8b4404	16	MEM_BLOCK_MEM2_CFG	MEM block protection configuration for MEM2
0x0d8b4406	16	MEM_BLOCK_ERROR_ADDR_LOW	MEM block protection violation's address (low)
0x0d8b4408	16	MEM_BLOCK_ERROR_ADDR_HIGH	MEM block protection violation's address (high)
0x0d8b440e	16	MEM_BLOCK_UNK	Unknown
0x0d8b442a	16	MEM_BLOCK_UNK	Unknown
0x0d8b442c	16	MEM_BLOCK_UNK	Unknown
0x0d8b44c4	16	MEM_BLOCK_UNK	Unknown
0x0d8b4472	16	MEM_BLOCK_ERROR_CID	MEM block protection violation's client ID
0x0d8b4474	16	MEM_BLOCK_ERROR	MEM block protection violation's state
0x0d8b4494	16	MEM_BLOCK_UNK	Unknown
0x0d8b4492	16	MEM_BLOCK_UNK	Unknown