Hardware/Latte registers

The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the Espresso. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.

Latte registers
Access
Espresso	Partial
Starbuck	Full
Registers
Base	0x0d800000
Length	0x800[check]
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	12
Latte	0,10,11,17,30,31,...[check]

Register list

Latte Registers
Address	Bits	Name	Description
0x0d800000	32	LT_IPC_PPCMSG	IPC
0x0d800004	32	LT_IPC_PPCCTRL
0x0d800008	32	LT_IPC_ARMMSG
0x0d80000c	32	LT_IPC_ARMCTRL
0x0d800010	32	LT_TIMER	Starbuck Timer
0x0d800014	32	LT_ALARM
0x0d800030	32	LT_PPCIRQFLAG	Latte_IRQ_Controller
0x0d800034	32	LT_PPCIRQMASK
0x0d800038	32	LT_ARMIRQFLAG
0x0d80003c	32	LT_ARMIRQMASK
0x0d800060	32	LT_MEMIRR	Memory control[check]
0x0d800064	32	LT_AHBPROT	Access control for the PPC to access devices on the AHB
0x0d800070	32	LT_EXICTRL	EXI PPC enable / control / other [check]
0x0d8000c0	32	LT_GPIOB_OUT	Latte GPIOs
0x0d8000c4	32	LT_GPIOB_DIR
0x0d8000c8	32	LT_GPIOB_IN
0x0d8000cc	32	LT_GPIOB_INTLVL
0x0d8000d0	32	LT_GPIOB_INTFLAG
0x0d8000d4	32	LT_GPIOB_INTMASK
0x0d8000d8	32	LT_GPIOB_INMIR
0x0d8000dc	32	LT_GPIO_ENABLE
0x0d8000e0	32	LT_GPIO_OUT
0x0d8000e4	32	LT_GPIO_DIR
0x0d8000e8	32	LT_GPIO_IN
0x0d8000ec	32	LT_GPIO_INTLVL
0x0d8000f0	32	LT_GPIO_INTFLAG
0x0d8000f4	32	LT_GPIO_INTMASK
0x0d8000f8	32	LT_GPIO_INMIR
0x0d8000fc	32	LT_GPIO_OWNER
0x0d800180	32	LT_DIFLAGS	Drive interface stuff[check]
0x0d80018c	32	LT_BOOT0	Maps boot0 [check]
0x0d800190	32	LT_CLOCKS	Clock stuff?
0x0d800194	32	LT_RESETS	System resets / power[check]
0x0d800198	32	LT_IFPOWER	Interfaces' power state (set by IOS-BSP)
0x0d8001dc	32	LT_SSPOWER	Subsystems' power state (set by IOS-BSP)
0x0d8001ec	32	LT_OTPCMD	OTP
0x0d8001f0	32	LT_OTPDATA
0x0d800214	32	LT_VERSION	Latte version
0x0d800400	32	LT_IPC_PPC0_PPCMSG	IPC (per-core)
0x0d800404	32	LT_IPC_PPC0_PPCCTRL
0x0d800408	32	LT_IPC_PPC0_ARMMSG
0x0d80040c	32	LT_IPC_PPC0_ARMCTRL
0x0d800410	32	LT_IPC_PPC1_PPCMSG
0x0d800414	32	LT_IPC_PPC1_PPCCTRL
0x0d800418	32	LT_IPC_PPC1_ARMMSG
0x0d80041c	32	LT_IPC_PPC1_ARMCTRL
0x0d800420	32	LT_IPC_PPC2_PPCMSG
0x0d800424	32	LT_IPC_PPC2_PPCCTRL
0x0d800428	32	LT_IPC_PPC2_ARMMSG
0x0d80042c	32	LT_IPC_PPC2_ARMCTRL
0x0d800520	32	LT_GPIOB_OUT2	Latte GPIOs (mirror?)
0x0d800524	32	LT_GPIOB_DIR2
0x0d800528	32	LT_GPIOB_IN2
0x0d80052c	32	LT_GPIOB_INTLVL2
0x0d800530	32	LT_GPIOB_INTFLAG2
0x0d800534	32	LT_GPIOB_INTMASK2
0x0d800538	32	LT_GPIOB_INMIR2
0x0d80053c	32	LT_GPIO_ENABLE2
0x0d800540	32	LT_GPIO_OUT2
0x0d800544	32	LT_GPIO_DIR2
0x0d800548	32	LT_GPIO_IN2
0x0d80054c	32	LT_GPIO_INTLVL2
0x0d800550	32	LT_GPIO_INTFLAG2
0x0d800554	32	LT_GPIO_INTMASK2
0x0d800558	32	LT_GPIO_INMIR2
0x0d80055c	32	LT_GPIO_OWNER2
0x0d8b4228	16	MEM_FLUSHREQ	AHB flush request
0x0d8b422a	16	MEM_FLUSHACK	AHB flush ack

General Registers

LT_BOOT0 (0x0d80018c)
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Access	?
Field
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Access	?	R/W		R/W	?
Field		DSKPLLSRC		BOOT0

This register at least controls the boot0 memory mapping and DSK PLL source.

Field	Description
BOOT0	Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on LT_MEMMIRR
DSKPLLSRC	According to STM, setting this to 00 "puts DSKPLL back to external reference"