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Hardware/Latte registers

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The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the Espresso. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.

Latte registers
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800000
Length???
Access size32 bits
Byte orderBig Endian
IRQs
Espresso12
Latte0,10,11,17,30,31,...[check]
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Register list

Latte Registers
Address Bits Name Description
0x0d800000 32 LT_IPC_PPCMSG_COMPAT IPC (for vWii)
0x0d800004 32 LT_IPC_PPCCTRL_COMPAT
0x0d800008 32 LT_IPC_ARMMSG_COMPAT
0x0d80000c 32 LT_IPC_ARMCTRL_COMPAT
0x0d800010 32 LT_TIMER Starbuck Timer
0x0d800014 32 LT_ALARM
0x0d800030 32 LT_INTSR_PPC_COMPAT Wood IRQs (for vWii)
0x0d800034 32 LT_INTMR_PPC_COMPAT
0x0d800038 32 LT_INTSR_ARM_COMPAT
0x0d80003c 32 LT_INTMR_ARM_COMPAT
0x0d800040 32 LT_INTMR_ARM2x_COMPAT
0x0d800044 32 UNKNOWN Unknown
0x0d800048 32 LT_AHB_WDG_STATUS AHB Watchdog status
0x0d80004c 32 LT_AHB_WDG_CONFIG AHB Watchdog configuration
0x0d800050 32 LT_AHB_DMA_STATUS AHB DMA transfer status
0x0d800054 32 LT_AHB_CPU_STATUS AHB CPU transfer status
0x0d800058 32 LT_ERROR Hardware error code
0x0d80005c 32 LT_ERROR_MASK Hardware error code mask
0x0d800060 32 LT_MEMIRR Memory control[check]
0x0d800064 32 LT_AHBPROT Access control for the PPC to access devices on the AHB
0x0d800068 32 UNKNOWN Unknown
0x0d80006c 32 UNKNOWN Unknown
0x0d800070 32 LT_EXICTRL EXI PPC enable / control / other [check]
0x0d800074 32 UNKNOWN Unknown
0x0d800088 32 UNKNOWN Unknown
0x0d8000c0 32 LT_GPIOE_OUT Latte GPIOs
0x0d8000c4 32 LT_GPIOE_DIR
0x0d8000c8 32 LT_GPIOE_IN
0x0d8000cc 32 LT_GPIOE_INTLVL
0x0d8000d0 32 LT_GPIOE_INTFLAG
0x0d8000d4 32 LT_GPIOE_INTMASK
0x0d8000d8 32 LT_GPIOE_INMIR
0x0d8000dc 32 LT_GPIO_ENABLE
0x0d8000e0 32 LT_GPIO_OUT
0x0d8000e4 32 LT_GPIO_DIR
0x0d8000e8 32 LT_GPIO_IN
0x0d8000ec 32 LT_GPIO_INTLVL
0x0d8000f0 32 LT_GPIO_INTFLAG
0x0d8000f4 32 LT_GPIO_INTMASK
0x0d8000f8 32 LT_GPIO_INMIR
0x0d8000fc 32 LT_GPIO_OWNER
0x0d800100 32 LT_AHB_UNK AHB specific registers
0x0d800104 32 LT_AHB_UNK
0x0d800108 32 LT_AHB_UNK
0x0d80010c 32 LT_AHB_UNK
0x0d800110 32 LT_AHB_UNK
0x0d800114 32 LT_AHB_UNK
0x0d800118 32 LT_AHB_UNK
0x0d80011c 32 LT_AHB_UNK
0x0d800120 32 LT_AHB_UNK
0x0d800124 32 LT_AHB_UNK
0x0d800130 32 LT_AHB_UNK
0x0d800134 32 LT_AHB_UNK
0x0d800138 32 LT_AHB_UNK
0x0d800140 32 LT_ARB_CFG AHB Arbiter configuration
0x0d800180 32 LT_DIFLAGS Drive interface flags (for vWii)
0x0d800184 32 LT_RESETS_AHB Resets for elements connected to the AHB
0x0d800188 32 LT_COMPAT_MEMCTRL_WORKAROUND Unknown
0x0d80018c 32 LT_BOOT0 Maps boot0 and controls a few other things
0x0d800190 32 LT_CLOCKINFO Clock information
0x0d800194 32 LT_RESETS_COMPAT System resets (for Wood based hardware)
0x0d800198 32 LT_CLOCKGATE_COMPAT Interfaces' clock gate (for Wood based hardware)
0x0d8001a8 32 LT_SATA_UNK Unknown
0x0d8001c8 32 LT_SATA_UNK Unknown
0x0d8001cc 32 LT_SATA_UNK Unknown
0x0d8001d0 32 LT_SATA_UNK Unknown
0x0d8001d8 32 UNKNOWN Unknown
0x0d8001dc 32 LT_IOPOWER Subsystems' power state
0x0d8001e0 32 LT_IOSTRENGTH_CTRL0 Subsystems' power strength control
0x0d8001e4 32 LT_IOSTRENGTH_CTRL1 Subsystems' power strength control
0x0d8001e8 32 LT_ACRCLK_STRENGTH_CTRL ACR chip's clock power strength
0x0d8001ec 32 LT_OTPCMD OTP
0x0d8001f0 32 LT_OTPDATA
0x0d800204 32 UNKNOWN Unknown
0x0d800214 32 LT_ASICREV_ACR ACR chip's revision ID (Hollywood/Bollywood)
0x0d800224 32 UNKNOWN Unknown
0x0d800250 32 UNKNOWN Unknown
0x0d800254 32 UNKNOWN Unknown
0x0d800258 32 UNKNOWN Unknown
0x0d800400 32 LT_IPC_PPC0_PPCMSG IPC (per-core, for Latte)
0x0d800404 32 LT_IPC_PPC0_PPCCTRL
0x0d800408 32 LT_IPC_PPC0_ARMMSG
0x0d80040c 32 LT_IPC_PPC0_ARMCTRL
0x0d800410 32 LT_IPC_PPC1_PPCMSG
0x0d800414 32 LT_IPC_PPC1_PPCCTRL
0x0d800418 32 LT_IPC_PPC1_ARMMSG
0x0d80041c 32 LT_IPC_PPC1_ARMCTRL
0x0d800420 32 LT_IPC_PPC2_PPCMSG
0x0d800424 32 LT_IPC_PPC2_PPCCTRL
0x0d800428 32 LT_IPC_PPC2_ARMMSG
0x0d80042c 32 LT_IPC_PPC2_ARMCTRL
0x0d800440 32 LT_INTSR_AHBALL_PPC0 Latte IRQs (per-core, for Latte)
0x0d800444 32 LT_INTSR_AHBLT_PPC0
0x0d800448 32 LT_INTMR_AHBALL_PPC0
0x0d80044c 32 LT_INTMR_AHBLT_PPC0
0x0d800450 32 LT_INTSR_AHBALL_PPC1
0x0d800454 32 LT_INTSR_AHBLT_PPC1
0x0d800458 32 LT_INTMR_AHBALL_PPC1
0x0d80045c 32 LT_INTMR_AHBLT_PPC1
0x0d800460 32 LT_INTSR_AHBALL_PPC2
0x0d800464 32 LT_INTSR_AHBLT_PPC2
0x0d800468 32 LT_INTMR_AHBALL_PPC2
0x0d80046c 32 LT_INTMR_AHBLT_PPC2
0x0d800470 32 LT_INTSR_AHBALL_ARM
0x0d800474 32 LT_INTSR_AHBLT_ARM
0x0d800478 32 LT_INTMR_AHBALL_ARM
0x0d80047c 32 LT_INTMR_AHBLT_ARM
0x0d800480 32 LT_INTMR_AHBALL_ARM2x
0x0d800484 32 LT_INTMR_AHBLT_ARM2x
0x0d8004a0 32 LT_AHB2_WDG_STATUS AHB2 Watchdog status
0x0d8004a4 32 LT_AHB2_DMA_STATUS AHB2 DMA transfer status
0x0d8004a8 32 LT_AHB2_CPU_STATUS AHB2 CPU transfer status
0x0d8004c8 32 UNKNOWN Unknown
0x0d8004cc 32 UNKNOWN Unknown
0x0d8004d0 32 UNKNOWN Unknown
0x0d8004d4 32 UNKNOWN Unknown
0x0d8004dc 32 UNKNOWN Unknown
0x0d8004e0 32 UNKNOWN Unknown
0x0d8004e4 32 UNKNOWN Unknown
0x0d800500 32 UNKNOWN Unknown
0x0d800504 32 UNKNOWN Unknown
0x0d800510 32 LT_OTPPROT Bitmask used to lock out chunks of OTP (0x20 bytes each)
0x0d800514 32 LT_SYSPROT Hardware sandbox for vWii mode
0x0d800520 32 LT_GPIOE2_OUT Latte GPIOs (second line)
0x0d800524 32 LT_GPIOE2_DIR
0x0d800528 32 LT_GPIOE2_IN
0x0d80052c 32 LT_GPIOE2_INTLVL
0x0d800530 32 LT_GPIOE2_INTFLAG
0x0d800534 32 LT_GPIOE2_INTMASK
0x0d800538 32 LT_GPIOE2_INMIR
0x0d80053c 32 LT_GPIO2_ENABLE
0x0d800540 32 LT_GPIO2_OUT
0x0d800544 32 LT_GPIO2_DIR
0x0d800548 32 LT_GPIO2_IN
0x0d80054c 32 LT_GPIO2_INTLVL
0x0d800550 32 LT_GPIO2_INTFLAG
0x0d800554 32 LT_GPIO2_INTMASK
0x0d800558 32 LT_GPIO2_INMIR
0x0d80055c 32 LT_GPIO2_OWNER
0x0d800570 32 LT_I2C_CLOCK I2C specific registers
0x0d800574 32 LT_I2C_INOUT_DATA
0x0d800578 32 LT_I2C_INOUT_CTRL
0x0d80057c 32 LT_I2C_INOUT_SIZE
0x0d800580 32 LT_I2C_INT_MASK
0x0d800584 32 LT_I2C_INT_STATE
0x0d8005a0 32 LT_ASICREV_CCR CCR chip revision ID (Latte)
0x0d8005a4 32 LT_DEBUG DEBUG mode flags
0x0d8005b0 32 LT_COMPAT_MEMCTRL_STATE Compat memory control mode (for vWii)
0x0d8005b4 32 LT_COMPAT_AHB_STATE Compat AHB mode (for vWii)
0x0d8005b8 32 LT_COMPAT_STEREO_OUT_SELECT Stereo configuration (for vWii)
0x0d8005bc 32 LT_IOP2X Unknown
0x0d8005c0 32 UNKNOWN Unknown
0x0d8005c8 32 LT_IOSTRENGTH_CTRL2 Subsystems' power strength control
0x0d8005cc 32 UNKNOWN Unknown
0x0d8005e0 32 LT_RESETS System resets (for Latte based hardware)
0x0d8005e4 32 LT_RESETS_AHMN Resets for elements connected to the AHB XN unit
0x0d8005e8 32 LT_CLOCKGATE Interfaces' clock gate (for Latte based hardware)
0x0d8005ec 32 LT_SYSPLL_CFG System PLL configuration
0x0d800620 32 LT_ABIF_CPLTL_OFFSET ASIC BIF (bus interface) Cpl Tl read/write offset
0x0d800624 32 LT_ABIF_CPLTL_DATA ASIC BIF (bus interface) Cpl Tl read/write data
0x0d800628 32 UNKNOWN Unknown
0x0d800640 32 LT_60XE_CFG 60Xe data bus configuration
0x0d800660 32 UNKNOWN Unknown
0x0d800640 32 UNKNOWN Unknown
0x0d800708 32 LT_DCCMPT Switch DC video mode (normal/compat)

General Registers

LT_ASICREV_ACR (0x0d800214)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access U
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R R
Field VERHI VERLO

This register contains the hardware revision of the Wood chipset (used for vWii mode). The IOSU also stores this value in a flag inside it's kernel's heap.
Hardware revision -> IOSU equivalent flag -> BSP hardware version
0x?? -> 0x00000000 -> BSP_HARDWARE_VERSION_UNKNOWN
0x00 -> 0x00000001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_1
0x10 -> 0x10000001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_2
0x?? -> 0x10100001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_PROD_FOR_WII
0x11 -> 0x10100008 -> BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO
0x?? -> 0x1010000C -> BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO_ESPRESSO
0x20 -> 0x20000001 -> BSP_HARDWARE_VERSION_BOLLYWOOD
0x21 -> 0x20100001 -> BSP_HARDWARE_VERSION_BOLLYWOOD_PROD_FOR_WII

Field Description
VERHI Version
VERLO Revision


LT_ASICREV_CCR (0x0d8005a0)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access U
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access U R R
Field VERHI VERLO

This register contains the hardware revision of the Latte chipset. The IOSU also stores this value in a flag inside it's kernel's heap.
Hardware revision -> IOSU equivalent flag -> BSP hardware version
0x10 -> 0x21100010 -> BSP_HARDWARE_VERSION_LATTE_A11_EV
0x10 -> 0x21100020 -> BSP_HARDWARE_VERSION_LATTE_A11_CAT
0x18 -> 0x21200010 -> BSP_HARDWARE_VERSION_LATTE_A12_EV
0x18 -> 0x21200020 -> BSP_HARDWARE_VERSION_LATTE_A12_CAT
0x21 -> 0x22100010 -> BSP_HARDWARE_VERSION_LATTE_A2X_EV
0x21 -> 0x22100020 -> BSP_HARDWARE_VERSION_LATTE_A2X_CAT
0x30 -> 0x23100010 -> BSP_HARDWARE_VERSION_LATTE_A3X_EV
0x30 -> 0x23100020 -> BSP_HARDWARE_VERSION_LATTE_A3X_CAT
0x30 -> 0x23100028 -> BSP_HARDWARE_VERSION_LATTE_A3X_CAFE
0x40 -> 0x24100010 -> BSP_HARDWARE_VERSION_LATTE_A4X_EV
0x40 -> 0x24100020 -> BSP_HARDWARE_VERSION_LATTE_A4X_CAT
0x40 -> 0x24100028 -> BSP_HARDWARE_VERSION_LATTE_A4X_CAFE
0x50 -> 0x25100010 -> BSP_HARDWARE_VERSION_LATTE_A5X_EV
0x50 -> 0x25100011 -> BSP_HARDWARE_VERSION_LATTE_A5X_EV_Y
0x50 -> 0x25100020 -> BSP_HARDWARE_VERSION_LATTE_A5X_CAT
0x50 -> 0x25100028 -> BSP_HARDWARE_VERSION_LATTE_A5X_CAFE
0x60 -> 0x26100010 -> BSP_HARDWARE_VERSION_LATTE_B1X_EV
0x60 -> 0x26100011 -> BSP_HARDWARE_VERSION_LATTE_B1X_EV_Y
0x60 -> 0x26100020 -> BSP_HARDWARE_VERSION_LATTE_B1X_CAT
0x60 -> 0x26100028 -> BSP_HARDWARE_VERSION_LATTE_B1X_CAFE

Field Description
VERHI Version
VERLO Revision


LT_BOOT0 (0x0d80018c)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access ?
Field
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ? R/W R/W ?
Field DSKPLLSRC BOOT0

This register at least controls the boot0 memory mapping and DSK PLL source.

Field Description
BOOT0 Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on LT_MEMMIRR
DSKPLLSRC According to STM, setting this to 00 "puts DSKPLL back to external reference"


LT_DEBUG (0x0d8005a4)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W ?
Field DEBUG
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register at least holds a flag related to DEBUG mode.

Field Description
DEBUG Ask for user input during the IOSU's boot sequence


LT_OTPPROT (0x0d800510)
  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Access R/W ?
Field BOOT1
  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access ?
Field

This register is a bitmask for locking out chunks of the OTP. Each bit clears out 0x20 bytes of the OTP starting from the bottom (bank 7 is 0xF0000000) to the top (bank 0 is 0x0000000F).

Field Description
BOOT1 Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7


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