Hardware/SHA-1 engine
| SHA-1 engine | |
| Access | |
|---|---|
| Espresso | None |
| Starbuck | Full |
| Registers | |
| Base | 0x0d030000, 0x0d190000 |
| Length | 0x1a |
| Access size | 32 bits |
| Byte order | Big Endian |
| IRQs | |
| Espresso | None |
| Latte | 3 |
The Latte's SHA-1 Engine calculates the SHA-1 compression function over a series of 64-byte data blocks and an initial 160-bit hash value, producing an output 160-bit SHA-1 hash. It does not perform SHA-1 input padding; this operation must be performed in software, and then an integer number of data blocks must be sent to the engine.
There are also traces of code inside IOS-CRYPTO that suggest the existence of a second engine named SHAS, probably only available in evaluation/debug units.
Register List
| SHA-1 Engine | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d030000 | 32 | SHA_CTRL | SHA-1 Control and Status |
| 0x0d030004 | 32 | SHA_SRC | Source memory address |
| 0x0d030008 | 32 | SHA_H0 | H0 hash value |
| 0x0d03000c | 32 | SHA_H1 | H1 hash value |
| 0x0d030010 | 32 | SHA_H2 | H2 hash value |
| 0x0d030014 | 32 | SHA_H3 | H3 hash value |
| 0x0d030018 | 32 | SHA_H4 | H4 hash value |
| SHAS-1 Engine | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d190000 | 32 | SHAS_CTRL | SHAS-1 Control and Status |
| 0x0d190004 | 32 | SHAS_SRC | Source memory address |
| 0x0d190008 | 32 | SHAS_H0 | H0 hash value |
| 0x0d19000c | 32 | SHAS_H1 | H1 hash value |
| 0x0d190010 | 32 | SHAS_H2 | H2 hash value |
| 0x0d190014 | 32 | SHAS_H3 | H3 hash value |
| 0x0d190018 | 32 | SHAS_H4 | H4 hash value |
Register Details
| SHA_CTRL (0x0d030000) | ||||||||||||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | R/W | R/W | U | ||||||||||||
| Field | EXEC | IRQ | ERR | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | W | ||||||||||||||
| Field | BLOCKS | |||||||||||||||
This register controls the state of the SHA-1 engine.
| Field | Description |
| EXEC | Write 1: initiate SHA-1 hashing Write 0: reset SHA-1 engine Read: SHA-1 engine busy |
| IRQ | Set to enable IRQ generation when hashing is complete |
| ERR | If set, SHA-1 error occurred (?)[check] |
| BLOCKS | Number of 64-byte blocks to process, minus one. 0 means one block. |
| SHA_SRC (0x0d030004) | ||
| 316 | 50 | |
| Access | R/W | U |
This register contains the DMA address of the data to be hashed. The address must be 64-byte aligned. The engine updates this register as it processes the blocks.
| SHA_H0 (0x0d030008) | |
| 310 | |
| Access | R/W |
| SHA_H1 (0x0d03000c) | |
| 310 | |
| Access | R/W |
| SHA_H2 (0x0d030010) | |
| 310 | |
| Access | R/W |
| SHA_H3 (0x0d030014) | |
| 310 | |
| Access | R/W |
| SHA_H4 (0x0d030018) | |
| 310 | |
| Access | R/W |
These registers contain the SHA-1 hash value. When starting to hash a new data string, they should be initialized to the following constants: 0x67452301 0xEFCDAB89 0x98BADCFE 0x10325476 0xC3D2E1F0. They can be preserved across operations to append more data to the hash. When the entire input string plus padding has been sent to the engine for processing, the value contained in these registers is the final SHA-1 Hash.