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Hardware/Processor interface (view source)
Revision as of 22:54, 20 August 2015
, 22:54, 20 August 2015Create basic Processor Interface page
{{Infobox MMIO
| ppc = Full
| base = 0x0c000000
| len = 0xc0000
| bits = 32
}}
==IRQ Sources==
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
|- style="background-color: #ddd;"
! IRQ
! Description
|-
| ||
|}
==Register List==
{{reglist|IPC}}
{{rla|0x0c000000|32|PI_INTSR_GLOBAL|Globally-triggered IRQs}}
{{rla|0x0c000004|32|PI_INTMR_GLOBAL|Globally-allowed IRQs}}
{{rla|0x0c000078|32|PI_INTSR_CPU0|Triggered IRQs for CPU0}}
{{rla|0x0c00007c|32|PI_INTMR_CPU0|Allowed IRQs for CPU0}}
{{rla|0x0c000080|32|PI_INTSR_CPU1|Triggered IRQs for CPU1}}
{{rla|0x0c000084|32|PI_INTMR_CPU1|Allowed IRQs for CPU1}}
{{rla|0x0c000088|32|PI_INTSR_CPU2|Triggered IRQs for CPU2}}
{{rla|0x0c00008c|32|PI_INTMR_CPU2|Allowed IRQs for CPU2}}
|}
==Register Details==
| ppc = Full
| base = 0x0c000000
| len = 0xc0000
| bits = 32
}}
==IRQ Sources==
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
|- style="background-color: #ddd;"
! IRQ
! Description
|-
| ||
|}
==Register List==
{{reglist|IPC}}
{{rla|0x0c000000|32|PI_INTSR_GLOBAL|Globally-triggered IRQs}}
{{rla|0x0c000004|32|PI_INTMR_GLOBAL|Globally-allowed IRQs}}
{{rla|0x0c000078|32|PI_INTSR_CPU0|Triggered IRQs for CPU0}}
{{rla|0x0c00007c|32|PI_INTMR_CPU0|Allowed IRQs for CPU0}}
{{rla|0x0c000080|32|PI_INTSR_CPU1|Triggered IRQs for CPU1}}
{{rla|0x0c000084|32|PI_INTMR_CPU1|Allowed IRQs for CPU1}}
{{rla|0x0c000088|32|PI_INTSR_CPU2|Triggered IRQs for CPU2}}
{{rla|0x0c00008c|32|PI_INTMR_CPU2|Allowed IRQs for CPU2}}
|}
==Register Details==