Hardware/Processor interface: Difference between revisions
< Hardware
Marionumber1 (talk | contribs) →IRQ Sources: Take probable IRQ numbers from http://pastebin.com/mAgkL9eW |
Marionumber1 (talk | contribs) →IRQ Sources: Add connections to IRQs |
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| Line 11: | Line 11: | ||
! IRQ | ! IRQ | ||
! Description | ! Description | ||
! Connection | |||
|- | |- | ||
|0 || Error | |0 || Error || Processor Interface | ||
|- | |- | ||
|1 || {{hw|DSP}} (all DSP IRQs) | |1 || {{hw|DSP}} (all DSP IRQs) || Processor Interface | ||
|- | |- | ||
|2 || {{hw|GX2}} | |2 || {{hw|GX2}} || Processor Interface (Latte) | ||
|- | |- | ||
|3 || GPIPPC (?) | |3 || GPIPPC (?) || AHB | ||
|- | |- | ||
|4 || {{hw|I2C}} | |4 || {{hw|I2C}} || AHB (Latte) | ||
|- | |- | ||
|5 || {{hw|Audio Interface}} (TV) | |5 || {{hw|Audio Interface}} (TV) || {{hw|DSP}} | ||
|- | |- | ||
|6 || {{hw|Audio Interface}} (Gamepad) | |6 || {{hw|Audio Interface}} (Gamepad) || {{hw|DSP}} (Latte) | ||
|- | |- | ||
|7 || ACC (?) | |7 || ACC (?) || {{hw|DSP}} | ||
|- | |- | ||
|8 || {{hw|DSP}} (again?) | |8 || {{hw|DSP}} (again?) || {{hw|DSP}} | ||
|- | |- | ||
|9 || {{hw|IPC}} (CPU0) | |9 || {{hw|IPC}} (CPU0) || AHB (Latte) | ||
|- | |- | ||
|10 || {{hw|IPC}} (CPU1) | |10 || {{hw|IPC}} (CPU1) || AHB (Latte) | ||
|- | |- | ||
|11 || {{hw|IPC}} (CPU2) | |11 || {{hw|IPC}} (CPU2) || AHB (Latte) | ||
|- | |- | ||
|12 || {{hw|Latte IRQs}} | |12 || {{hw|Latte IRQs}} || Processor Interface (Latte) | ||
|} | |} | ||
Revision as of 01:48, 21 August 2015
| Processor interface | |
| Access | |
|---|---|
| Espresso | Full |
| Starbuck | None |
| Registers | |
| Base | 0x0c000000 |
| Length | 0xc0000 |
| Access size | 32 bits |
| Byte order | Big Endian |
IRQ Sources
| IRQ | Description | Connection |
|---|---|---|
| 0 | Error | Processor Interface |
| 1 | DSP (all DSP IRQs) | Processor Interface |
| 2 | GX2 | Processor Interface (Latte) |
| 3 | GPIPPC (?) | AHB |
| 4 | I2C | AHB (Latte) |
| 5 | Audio Interface (TV) | DSP |
| 6 | Audio Interface (Gamepad) | DSP (Latte) |
| 7 | ACC (?) | DSP |
| 8 | DSP (again?) | DSP |
| 9 | IPC (CPU0) | AHB (Latte) |
| 10 | IPC (CPU1) | AHB (Latte) |
| 11 | IPC (CPU2) | AHB (Latte) |
| 12 | Latte IRQs | Processor Interface (Latte) |
Register List
| Processor Interface | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0c000000 | 32 | PI_INTSR_GLOBAL | Globally-triggered IRQs |
| 0x0c000004 | 32 | PI_INTMR_GLOBAL | Globally-allowed IRQs |
| 0x0c000078 | 32 | PI_INTSR_CPU0 | Triggered IRQs for CPU0 |
| 0x0c00007c | 32 | PI_INTMR_CPU0 | Allowed IRQs for CPU0 |
| 0x0c000080 | 32 | PI_INTSR_CPU1 | Triggered IRQs for CPU1 |
| 0x0c000084 | 32 | PI_INTMR_CPU1 | Allowed IRQs for CPU1 |
| 0x0c000088 | 32 | PI_INTSR_CPU2 | Triggered IRQs for CPU2 |
| 0x0c00008c | 32 | PI_INTMR_CPU2 | Allowed IRQs for CPU2 |