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Hardware/Latte registers (view source)
Revision as of 23:55, 27 October 2015
, 23:55, 27 October 2015Creating registers page
{{Infobox MMIO
| arm = Full
| ppc = Partial
| base = 0x0d800000
| len = 0x800{{check}}
| bits = 32
| ppcirq = 12
| hwdirq = 0,10,11,17,30,31,...{{check}}
}}
The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the {{Espresso}}. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.
== Register list ==
{{reglist|Latte Registers}}
{{rld|0x0d800000|32|LT_IPC_PPCMSG|[[Hardware/IPC|IPC]]|drs=4}}
{{rld|0x0d800004|32|LT_IPC_PPCCTRL}}
{{rld|0x0d800008|32|LT_IPC_ARMMSG}}
{{rld|0x0d80000c|32|LT_IPC_ARMCTRL}}
{{rld|0x0d800010|32|LT_TIMER|[[Hardware/Starbuck Timer|Starbuck Timer]]|drs=2}}
{{rld|0x0d800014|32|LT_ALARM}}
{{rld|0x0d800030|32|LT_PPCIRQFLAG|[[Hardware/Latte_IRQ_Controller|Latte_IRQ_Controller]]|drs=4}}
{{rld|0x0d800034|32|LT_PPCIRQMASK}}
{{rld|0x0d800038|32|LT_ARMIRQFLAG}}
{{rld|0x0d80003c|32|LT_ARMIRQMASK}}
{{rld|0x0d800060|32|LT_MEMIRR|Memory control{{check}}}}
{{rld|0x0d800064|32|LT_AHBPROT|Access control for the PPC to access devices on the AHB}}
{{rla|0x0d800070|32|LT_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
{{rld|0x0d8000c0|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
{{rld|0x0d8000c4|32|LT_GPIOB_DIR}}
{{rld|0x0d8000c8|32|LT_GPIOB_IN}}
{{rld|0x0d8000cc|32|LT_GPIOB_INTLVL}}
{{rld|0x0d8000d0|32|LT_GPIOB_INTFLAG}}
{{rld|0x0d8000d4|32|LT_GPIOB_INTMASK}}
{{rld|0x0d8000d8|32|LT_GPIOB_INMIR}}
{{rld|0x0d8000dc|32|LT_GPIO_ENABLE}}
{{rld|0x0d8000e0|32|LT_GPIO_OUT}}
{{rld|0x0d8000e4|32|LT_GPIO_DIR}}
{{rld|0x0d8000e8|32|LT_GPIO_IN}}
{{rld|0x0d8000ec|32|LT_GPIO_INTLVL}}
{{rld|0x0d8000f0|32|LT_GPIO_INTFLAG}}
{{rld|0x0d8000f4|32|LT_GPIO_INTMASK}}
{{rld|0x0d8000f8|32|LT_GPIO_INMIR}}
{{rld|0x0d8000fc|32|LT_GPIO_OWNER}}
{{rla|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
{{rla|0x0d800190|32|LT_CLOCKS|Clock stuff?}}
{{rla|0x0d800194|32|LT_RESETS|System resets / power{{check}}}}
{{rld|0x0d800198|32|LT_IFPOWER|Interfaces' power state (set by IOS-BSP)}}
{{rld|0x0d8001dc|32|LT_SSPOWER|Subsystems' power state (set by IOS-BSP)}}
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001f0|32|LT_OTPDATA}}
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}
{{rld|0x0d800528|32|LT_GPIOB_IN2}}
{{rld|0x0d80052c|32|LT_GPIOB_INTLVL2}}
{{rld|0x0d800530|32|LT_GPIOB_INTFLAG2}}
{{rld|0x0d800534|32|LT_GPIOB_INTMASK2}}
{{rld|0x0d800538|32|LT_GPIOB_INMIR2}}
{{rld|0x0d80053c|32|LT_GPIO_ENABLE2}}
{{rld|0x0d800540|32|LT_GPIO_OUT2}}
{{rld|0x0d800544|32|LT_GPIO_DIR2}}
{{rld|0x0d800548|32|LT_GPIO_IN2}}
{{rld|0x0d80054c|32|LT_GPIO_INTLVL2}}
{{rld|0x0d800550|32|LT_GPIO_INTFLAG2}}
{{rld|0x0d800554|32|LT_GPIO_INTMASK2}}
{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
|}
== General Registers ==
{{reg32 | LT_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 4 |
|16 |
|? |
| ||
|1|2 |1 |12 |
|?|R/W|R/W | ? |
| |DSKPLLSRC|BOOT0| |
}}
This register at least controls the boot0 memory mapping and DSK PLL source.
{{regdesc
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on LT_MEMMIRR
|DSKPLLSRC|According to STM, setting this to 00 "puts DSKPLL back to external reference"
}}
{{hwstub}}
| arm = Full
| ppc = Partial
| base = 0x0d800000
| len = 0x800{{check}}
| bits = 32
| ppcirq = 12
| hwdirq = 0,10,11,17,30,31,...{{check}}
}}
The Latte chipset includes a large register area including many miscellaneous controls. Some of these registers can be accessed by the {{Espresso}}. Address bit 23 (0x00800000) controls the permission: if it is set, then the registers are accessed with Starbuck's permission (full access). If it is clear, only the PPC subset of the registers is visible. From the PPC, the state of this bit is irrelevant, which suggests that it is forced to zero internally in one of the buses.
== Register list ==
{{reglist|Latte Registers}}
{{rld|0x0d800000|32|LT_IPC_PPCMSG|[[Hardware/IPC|IPC]]|drs=4}}
{{rld|0x0d800004|32|LT_IPC_PPCCTRL}}
{{rld|0x0d800008|32|LT_IPC_ARMMSG}}
{{rld|0x0d80000c|32|LT_IPC_ARMCTRL}}
{{rld|0x0d800010|32|LT_TIMER|[[Hardware/Starbuck Timer|Starbuck Timer]]|drs=2}}
{{rld|0x0d800014|32|LT_ALARM}}
{{rld|0x0d800030|32|LT_PPCIRQFLAG|[[Hardware/Latte_IRQ_Controller|Latte_IRQ_Controller]]|drs=4}}
{{rld|0x0d800034|32|LT_PPCIRQMASK}}
{{rld|0x0d800038|32|LT_ARMIRQFLAG}}
{{rld|0x0d80003c|32|LT_ARMIRQMASK}}
{{rld|0x0d800060|32|LT_MEMIRR|Memory control{{check}}}}
{{rld|0x0d800064|32|LT_AHBPROT|Access control for the PPC to access devices on the AHB}}
{{rla|0x0d800070|32|LT_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
{{rld|0x0d8000c0|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
{{rld|0x0d8000c4|32|LT_GPIOB_DIR}}
{{rld|0x0d8000c8|32|LT_GPIOB_IN}}
{{rld|0x0d8000cc|32|LT_GPIOB_INTLVL}}
{{rld|0x0d8000d0|32|LT_GPIOB_INTFLAG}}
{{rld|0x0d8000d4|32|LT_GPIOB_INTMASK}}
{{rld|0x0d8000d8|32|LT_GPIOB_INMIR}}
{{rld|0x0d8000dc|32|LT_GPIO_ENABLE}}
{{rld|0x0d8000e0|32|LT_GPIO_OUT}}
{{rld|0x0d8000e4|32|LT_GPIO_DIR}}
{{rld|0x0d8000e8|32|LT_GPIO_IN}}
{{rld|0x0d8000ec|32|LT_GPIO_INTLVL}}
{{rld|0x0d8000f0|32|LT_GPIO_INTFLAG}}
{{rld|0x0d8000f4|32|LT_GPIO_INTMASK}}
{{rld|0x0d8000f8|32|LT_GPIO_INMIR}}
{{rld|0x0d8000fc|32|LT_GPIO_OWNER}}
{{rla|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
{{rla|0x0d800190|32|LT_CLOCKS|Clock stuff?}}
{{rla|0x0d800194|32|LT_RESETS|System resets / power{{check}}}}
{{rld|0x0d800198|32|LT_IFPOWER|Interfaces' power state (set by IOS-BSP)}}
{{rld|0x0d8001dc|32|LT_SSPOWER|Subsystems' power state (set by IOS-BSP)}}
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001f0|32|LT_OTPDATA}}
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}
{{rld|0x0d800528|32|LT_GPIOB_IN2}}
{{rld|0x0d80052c|32|LT_GPIOB_INTLVL2}}
{{rld|0x0d800530|32|LT_GPIOB_INTFLAG2}}
{{rld|0x0d800534|32|LT_GPIOB_INTMASK2}}
{{rld|0x0d800538|32|LT_GPIOB_INMIR2}}
{{rld|0x0d80053c|32|LT_GPIO_ENABLE2}}
{{rld|0x0d800540|32|LT_GPIO_OUT2}}
{{rld|0x0d800544|32|LT_GPIO_DIR2}}
{{rld|0x0d800548|32|LT_GPIO_IN2}}
{{rld|0x0d80054c|32|LT_GPIO_INTLVL2}}
{{rld|0x0d800550|32|LT_GPIO_INTFLAG2}}
{{rld|0x0d800554|32|LT_GPIO_INTMASK2}}
{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
|}
== General Registers ==
{{reg32 | LT_BOOT0 | addr = 0x0d80018c | hifields = 1 | lofields = 4 |
|16 |
|? |
| ||
|1|2 |1 |12 |
|?|R/W|R/W | ? |
| |DSKPLLSRC|BOOT0| |
}}
This register at least controls the boot0 memory mapping and DSK PLL source.
{{regdesc
|BOOT0|Disable boot0 mapping to either x'fffe_0000 or x'ffff_0000 depending on LT_MEMMIRR
|DSKPLLSRC|According to STM, setting this to 00 "puts DSKPLL back to external reference"
}}
{{hwstub}}