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Line 35:
Line 35: − + − + − + − + − + − + − + Line 64:
Line 64: + − + − + − + − + − + − + − + − + − + − + Line 111:
Line 112: − + − + − + − + − + − + − + − + − + − + − + − + − + − + Line 144:
Line 145: − + − + − + − + − + − + − + − + − + − + − +
Hardware/Latte registers (view source)
Revision as of 23:23, 7 November 2015
, 23:23, 7 November 2015More registers and some corrections
{{rld|0x0d800074|32|UNKNOWN|Unknown}}
{{rld|0x0d800074|32|UNKNOWN|Unknown}}
{{rld|0x0d800088|32|UNKNOWN|DDR?}}
{{rld|0x0d800088|32|UNKNOWN|DDR?}}
{{rld|0x0d8000c0|32|LT_GPIOB_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
{{rld|0x0d8000c0|32|LT_GPIOE_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
{{rld|0x0d8000c4|32|LT_GPIOB_DIR}}
{{rld|0x0d8000c4|32|LT_GPIOE_DIR}}
{{rld|0x0d8000c8|32|LT_GPIOB_IN}}
{{rld|0x0d8000c8|32|LT_GPIOE_IN}}
{{rld|0x0d8000cc|32|LT_GPIOB_INTLVL}}
{{rld|0x0d8000cc|32|LT_GPIOE_INTLVL}}
{{rld|0x0d8000d0|32|LT_GPIOB_INTFLAG}}
{{rld|0x0d8000d0|32|LT_GPIOE_INTFLAG}}
{{rld|0x0d8000d4|32|LT_GPIOB_INTMASK}}
{{rld|0x0d8000d4|32|LT_GPIOE_INTMASK}}
{{rld|0x0d8000d8|32|LT_GPIOB_INMIR}}
{{rld|0x0d8000d8|32|LT_GPIOE_INMIR}}
{{rld|0x0d8000dc|32|LT_GPIO_ENABLE}}
{{rld|0x0d8000dc|32|LT_GPIO_ENABLE}}
{{rld|0x0d8000e0|32|LT_GPIO_OUT}}
{{rld|0x0d8000e0|32|LT_GPIO_OUT}}
{{rld|0x0d800134|32|LT_AHB_UNK12}}
{{rld|0x0d800134|32|LT_AHB_UNK12}}
{{rld|0x0d800138|32|LT_AHB_UNK13}}
{{rld|0x0d800138|32|LT_AHB_UNK13}}
{{rld|0x0d800140|32|LT_WORKAROUNDS|Unknown}}
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
{{rld|0x0d800184|32|LT_UNKFLAGS|Unknown flags}}
{{rld|0x0d800184|32|LT_UNKFLAGS|Unknown flags}}
{{rld|0x0d800188|32|UNKNOWN|Unknown}}
{{rld|0x0d800188|32|UNKNOWN|Unknown}}
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
{{rld|0x0d800190|32|LT_CLOCKS|Clock stuff?}}
{{rld|0x0d800190|32|LT_CLOCKINFO|Clock information}}
{{rld|0x0d800194|32|LT_RESETS|System resets / power{{check}}}}
{{rld|0x0d800194|32|LT_RESETS|System resets {{check}}}}
{{rld|0x0d800198|32|LT_IFPOWER|Interfaces' power state (set by IOS-BSP)}}
{{rld|0x0d800198|32|LT_CLOCKGATE|Interfaces' clock gate}}
{{rld|0x0d8001a8|32|UNKNOWN|Unknown}}
{{rld|0x0d8001a8|32|LT_SATAPLL_UNK1|Unknown}}
{{rld|0x0d8001c8|32|UNKNOWN|Unknown}}
{{rld|0x0d8001c8|32|LT_SATAPLL_UNK2|Unknown}}
{{rld|0x0d8001cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8001cc|32|LT_SATAPLL_UNK3|Unknown}}
{{rld|0x0d8001d0|32|UNKNOWN|Unknown}}
{{rld|0x0d8001d0|32|LT_SATAPLL_UNK4|Unknown}}
{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
{{rld|0x0d8001dc|32|LT_SSPOWER|Subsystems' power state (set by IOS-BSP)}}
{{rld|0x0d8001dc|32|LT_IOPOWER|Subsystems' power state}}
{{rld|0x0d8001e0|32|UNKNOWN|Unknown}}
{{rld|0x0d8001e0|32|LT_IOSTRENGTH1|Subsystems' power strength}}
{{rld|0x0d8001e4|32|UNKNOWN|Unknown}}
{{rld|0x0d8001e4|32|LT_IOSTRENGTH2|Subsystems' power strength}}
{{rld|0x0d8001e8|32|UNKNOWN|Unknown}}
{{rld|0x0d8001e8|32|UNKNOWN|Unknown}}
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
{{rld|0x0d800468|32|LT_INTMR_AHBALL_PPC2}}
{{rld|0x0d800468|32|LT_INTMR_AHBALL_PPC2}}
{{rld|0x0d80046c|32|LT_INTMR_AHBLT_PPC2}}
{{rld|0x0d80046c|32|LT_INTMR_AHBLT_PPC2}}
{{rld|0x0d800470|32|LT_INTSR_ARM_OLD|Old mirror?}}
{{rld|0x0d800470|32|LT_INTSR_ARM2|Unknown duplicate}}
{{rld|0x0d800474|32|LT_GPIO_INTFLAG_OLD|Old mirror?}}
{{rld|0x0d800474|32|LT_GPIO_INTFLAG2|Unknown duplicate}}
{{rld|0x0d800478|32|LT_INTMR_ARM_OLD|Old mirror?}}
{{rld|0x0d800478|32|LT_INTMR_ARM2|Unknown duplicate}}
{{rld|0x0d80047c|32|LT_GPIO_INTMASK_OLD|Old mirror?}}
{{rld|0x0d80047c|32|LT_GPIO_INTMASK2|Unknown duplicate}}
{{rld|0x0d800480|32|UNKNOWN|Unknown}}
{{rld|0x0d800480|32|UNKNOWN|Unknown}}
{{rld|0x0d800484|32|UNKNOWN|Unknown}}
{{rld|0x0d800484|32|UNKNOWN|Unknown}}
{{rld|0x0d8004a4|32|LT_SYSPROTDRV2_UNK1|System protection driver (mirror?)|drs=2}}
{{rld|0x0d8004a4|32|LT_SYSPROTDRV_UNK5|System protection driver (mirror?)|drs=2}}
{{rld|0x0d8004a8|32|LT_SYSPROTDRV2_UNK1}}
{{rld|0x0d8004a8|32|LT_SYSPROTDRV_UNK6}}
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
{{rld|0x0d800510|32|LT_PANIC_UNK|Something for panic}}
{{rld|0x0d800510|32|LT_PANIC|Something for panic}}
{{rld|0x0d800520|32|LT_GPIOB_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
{{rld|0x0d800520|32|LT_GPIOE_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
{{rld|0x0d800524|32|LT_GPIOB_DIR2}}
{{rld|0x0d800524|32|LT_GPIOE_DIR2}}
{{rld|0x0d800528|32|LT_GPIOB_IN2}}
{{rld|0x0d800528|32|LT_GPIOE_IN2}}
{{rld|0x0d80052c|32|LT_GPIOB_INTLVL2}}
{{rld|0x0d80052c|32|LT_GPIOE_INTLVL2}}
{{rld|0x0d800530|32|LT_GPIOB_INTFLAG2}}
{{rld|0x0d800530|32|LT_GPIOE_INTFLAG2}}
{{rld|0x0d800534|32|LT_GPIOB_INTMASK2}}
{{rld|0x0d800534|32|LT_GPIOE_INTMASK2}}
{{rld|0x0d800538|32|LT_GPIOB_INMIR2}}
{{rld|0x0d800538|32|LT_GPIOE_INMIR2}}
{{rld|0x0d80053c|32|LT_GPIO_ENABLE2}}
{{rld|0x0d80053c|32|LT_GPIO_ENABLE2}}
{{rld|0x0d800540|32|LT_GPIO_OUT2}}
{{rld|0x0d800540|32|LT_GPIO_OUT2}}
{{rld|0x0d800580|32|UNKNOWN|Unknown}}
{{rld|0x0d800580|32|UNKNOWN|Unknown}}
{{rld|0x0d800584|32|UNKNOWN|Unknown}}
{{rld|0x0d800584|32|UNKNOWN|Unknown}}
{{rld|0x0d8005a0|32|UNKNOWN|Unknown}}
{{rld|0x0d8005a0|32|LT_ASICREV|ASIC revision}}
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
{{rld|0x0d8005b0|32|UNKNOWN|Unknown}}
{{rld|0x0d8005b0|32|UNKNOWN|Unknown}}
{{rld|0x0d8005b8|32|UNKNOWN|Unknown}}
{{rld|0x0d8005b8|32|LT_STEREO_OUT_SELECT|Stereo mode selector}}
{{rld|0x0d8005bc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005bc|32|LT_IOP2X|Unknown}}
{{rld|0x0d8005c8|32|UNKNOWN|Unknown}}
{{rld|0x0d8005c8|32|LT_MISC|Unknown}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
{{rld|0x0d8005e4|32|UNKNOWN|Unknown}}
{{rld|0x0d8005e4|32|LT_SATASUBSYS|Related to the SATA subsystem}}
{{rla|0x0d8005e0|32|LT_POWER|Power changes?}}
{{rla|0x0d8005e0|32|LT_RESETS2|System resets (mirror)}}
{{rld|0x0d8005ec|32|UNKNOWN|Unknown}}
{{rld|0x0d8005ec|32|LT_SYSPLL_UNK1|Unknown}}
{{rld|0x0d800620|32|UNKNOWN|Unknown}}
{{rld|0x0d800620|32|LT_SYSPLL_UNK2|Unknown}}
{{rld|0x0d800624|32|UNKNOWN|Unknown}}
{{rld|0x0d800624|32|LT_SYSPLL_UNK3|Unknown}}
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
{{rld|0x0d800640|32|LT_60XE_DATA_STREAMING|Unknown}}
{{rld|0x0d800660|32|UNKNOWN|Unknown}}
{{rld|0x0d800660|32|UNKNOWN|Unknown}}
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
{{rld|0x0d800708|32|UNKNOWN|Unknown}}
{{rld|0x0d800708|32|LT_DCCMPT|Switch DC video mode (normal/compat)}}
{{rld|0x0d8b4226|16|MEM_UNK1|Unknown}}
{{rld|0x0d8b4226|16|MEM_UNK1|Unknown}}
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}