In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

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Hardware/Latte registers (view source)

Revision as of 17:29, 3 February 2016

1,985 bytes added ,  17:29, 3 February 2016
More registers' documentation
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{{rld|0x0d800070|32|LT_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
 
{{rld|0x0d800070|32|LT_EXICTRL|[[Hardware/EXI|EXI]] PPC enable / control / other {{check}}}}
 
{{rld|0x0d800074|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800074|32|UNKNOWN|Unknown}}
−
{{rld|0x0d800088|32|UNKNOWN|DDR?}}
+
{{rld|0x0d800088|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8000c0|32|LT_GPIOE_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
 
{{rld|0x0d8000c0|32|LT_GPIOE_OUT|[[Hardware/Latte GPIOs|Latte GPIOs]]|drs=16}}
 
{{rld|0x0d8000c4|32|LT_GPIOE_DIR}}
 
{{rld|0x0d8000c4|32|LT_GPIOE_DIR}}
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{{rld|0x0d800134|32|LT_AHB_UNK12}}
 
{{rld|0x0d800134|32|LT_AHB_UNK12}}
 
{{rld|0x0d800138|32|LT_AHB_UNK13}}
 
{{rld|0x0d800138|32|LT_AHB_UNK13}}
−
{{rld|0x0d800140|32|LT_WORKAROUNDS|Unknown}}
+
{{rld|0x0d800140|32|LT_ARB_CFG|Unknown}}
 
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
 
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
−
{{rld|0x0d800184|32|LT_UNKFLAGS|Unknown flags}}
+
{{rld|0x0d800184|32|LT_AHB_RESETS|Unknown}}
−
{{rld|0x0d800188|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800188|32|LT_COMPAT_UNK1|Unknown}}
 
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
 
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
 
{{rld|0x0d800190|32|LT_CLOCKINFO|Clock information}}
 
{{rld|0x0d800190|32|LT_CLOCKINFO|Clock information}}
 
{{rld|0x0d800194|32|LT_RESETS|System resets {{check}}}}
 
{{rld|0x0d800194|32|LT_RESETS|System resets {{check}}}}
−
{{rld|0x0d800198|32|LT_CLOCKGATE|Interfaces' clock gate}}
+
{{rld|0x0d800198|32|LT_CLOCKGATE1|Interfaces' clock gate}}
 
{{rld|0x0d8001a8|32|LT_SATAPLL_UNK1|Unknown}}
 
{{rld|0x0d8001a8|32|LT_SATAPLL_UNK1|Unknown}}
 
{{rld|0x0d8001c8|32|LT_SATAPLL_UNK2|Unknown}}
 
{{rld|0x0d8001c8|32|LT_SATAPLL_UNK2|Unknown}}
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{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8001dc|32|LT_IOPOWER|Subsystems' power state}}
 
{{rld|0x0d8001dc|32|LT_IOPOWER|Subsystems' power state}}
−
{{rld|0x0d8001e0|32|LT_IOSTRENGTH1|Subsystems' power strength}}
+
{{rld|0x0d8001e0|32|LT_IOSTRENGTH_CTRL0|Subsystems' power strength}}
−
{{rld|0x0d8001e4|32|LT_IOSTRENGTH2|Subsystems' power strength}}
+
{{rld|0x0d8001e4|32|LT_IOSTRENGTH_CTRL1|Subsystems' power strength}}
−
{{rld|0x0d8001e8|32|UNKNOWN|Unknown}}
+
{{rld|0x0d8001e8|32|LT_ACRCLK_STRENGTH_CTRL|ACR clock's power strength}}
 
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001f0|32|LT_OTPDATA}}
 
{{rld|0x0d8001f0|32|LT_OTPDATA}}
 
{{rld|0x0d800204|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800204|32|UNKNOWN|Unknown}}
−
{{rla|0x0d800214|32|LT_VERSION|Latte version}}
+
{{rla|0x0d800214|32|LT_ASICREV_ACR|ACR chip revision ID (Hollywood)}}
 
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
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{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
−
{{rla|0x0d800510|32|LT_OTPPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each).}}
+
{{rla|0x0d800510|32|LT_OTPPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each)}}
 
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for vWii mode}}
 
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for vWii mode}}
 
{{rld|0x0d800520|32|LT_GPIOE_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
 
{{rld|0x0d800520|32|LT_GPIOE_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
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{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
 
{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
−
{{rld|0x0d800570|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800570|32|LT_I2C_UNK1|I2C specific registers|drs=6}}
−
{{rld|0x0d800574|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800574|32|LT_I2C_INOUT_DATA}}
−
{{rld|0x0d800578|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800578|32|LT_I2C_INOUT_CTRL}}
−
{{rld|0x0d80057c|32|UNKNOWN|Unknown}}
+
{{rld|0x0d80057c|32|LT_I2C_INOUT_SIZE}}
−
{{rld|0x0d800580|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800580|32|LT_I2C_INT_MASK}}
−
{{rld|0x0d800584|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800584|32|LT_I2C_INT_STATE}}
−
{{rld|0x0d8005a0|32|LT_ASICREV|ASIC revision}}
+
{{rla|0x0d8005a0|32|LT_ASICREV_CCR|CCR chip revision ID (Latte)}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
−
{{rld|0x0d8005b0|32|UNKNOWN|Unknown}}
+
{{rld|0x0d8005b0|32|LT_COMPAT_MEMCTRL|Compat mode registers|drs=5}}
−
{{rld|0x0d8005b8|32|LT_STEREO_OUT_SELECT|Stereo mode selector}}
+
{{rld|0x0d8005b4|32|LT_COMPAT_AHB}}
−
{{rld|0x0d8005bc|32|LT_IOP2X|Unknown}}
+
{{rld|0x0d8005b8|32|LT_COMPAT_STEREO_OUT_SELECT}}
−
{{rld|0x0d8005c8|32|LT_MISC|Unknown}}
+
{{rld|0x0d8005bc|32|LT_IOP2X}}
 +
{{rld|0x0d8005c0|32|LT_COMPAT_UNK2}}
 +
{{rld|0x0d8005c8|32|LT_IOSTRENGTH_CTRL2|Subsystems' power strength}}
 
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
−
{{rld|0x0d8005e4|32|LT_SATASUBSYS|Related to the SATA subsystem}}
+
{{rld|0x0d8005e0|32|LT_SATASUBSYS|Related to the SATA subsystem}}
−
{{rla|0x0d8005e0|32|LT_RESETS2|System resets (mirror)}}
+
{{rld|0x0d8005e4|32|LT_AHMN_RESETS|Unknown}}
−
{{rld|0x0d8005ec|32|LT_SYSPLL_UNK1|Unknown}}
+
{{rld|0x0d8005e8|32|LT_CLOCKGATE2|Unknown}}
−
{{rld|0x0d800620|32|LT_SYSPLL_UNK2|Unknown}}
+
{{rld|0x0d8005ec|32|LT_SYSPLL_UNK|SYSPLL registers|drs=3}}
−
{{rld|0x0d800624|32|LT_SYSPLL_UNK3|Unknown}}
+
{{rld|0x0d800620|32|LT_SYSPLL_OFFSET}}
 +
{{rld|0x0d800624|32|LT_SYSPLL_DATA}}
 
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800640|32|LT_60XE_DATA_STREAMING|Unknown}}
 
{{rld|0x0d800640|32|LT_60XE_DATA_STREAMING|Unknown}}
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{{rld|0x0d800640|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800708|32|LT_DCCMPT|Switch DC video mode (normal/compat)}}
 
{{rld|0x0d800708|32|LT_DCCMPT|Switch DC video mode (normal/compat)}}
−
{{rld|0x0d8b4226|16|MEM_UNK1|Unknown}}
  −
{{rld|0x0d8b4228|16|MEM_FLUSHREQ|AHB flush request}}
  −
{{rld|0x0d8b422a|16|MEM_FLUSHACK|AHB flush ack}}
  −
{{rld|0x0d8b42c4|16|MEM_UNK2|Unknown}}
  −
{{rld|0x0d8b42c6|16|MEM_UNK3|Unknown}}
  −
{{rld|0x0d8b4300|16|MEM_UNK4|Unknown}}
  −
{{rld|0x0d8b4302|16|MEM_UNK5|Unknown}}
   
|}
 
|}
    
== General Registers ==
 
== General Registers ==
−
{{reg32 | HW_VERSION | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
+
{{reg32 | LT_ASICREV_ACR | addr = 0x0d800214 | hifields = 1 | lofields = 3 |
 +
|16          |
 +
|U            |
 +
|            ||
 +
|8|4    |4    |
 +
|U|R    |R    |
 +
| |VERHI|VERLO|
 +
}}
 +
This register contains the hardware revision of the Hollywood chipset (used for vWii mode). The IOSU also stores this value in a flag inside it's kernel's heap.<br>
 +
Hardware revision -> IOSU equivalent flag -> BSP hardware version<br>
 +
0x?? -> 0x00000000 -> BSP_HARDWARE_VERSION_UNKNOWN<br>
 +
0x00 -> 0x00000001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_1<br>
 +
0x10 -> 0x10000001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_ENG_SAMPLE_2<br>
 +
0x?? -> 0x10100001 -> BSP_HARDWARE_VERSION_HOLLYWOOD_PROD_FOR_WII<br>
 +
0x11 -> 0x10100008 -> BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO<br>
 +
0x?? -> 0x1010000C -> BSP_HARDWARE_VERSION_HOLLYWOOD_CORTADO_ESPRESSO<br>
 +
0x20 -> 0x20000001 -> BSP_HARDWARE_VERSION_BOLLYWOOD<br>
 +
0x21 -> 0x20100001 -> BSP_HARDWARE_VERSION_BOLLYWOOD_PROD_FOR_WII<br>
 +
{{regdesc
 +
|VERHI|Version
 +
|VERLO|Revision
 +
}}
 +
 
 +
{{reg32 | LT_ASICREV_CCR | addr = 0x0d8005a0 | hifields = 1 | lofields = 3 |
 
|16          |
 
|16          |
 
|U            |
 
|U            |
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}}
 
}}
 
This register contains the hardware revision of the Latte chipset. The IOSU also stores this value in a flag inside it's kernel's heap.<br>
 
This register contains the hardware revision of the Latte chipset. The IOSU also stores this value in a flag inside it's kernel's heap.<br>
−
Hardware revision -> IOSU equivalent flag<br>
+
Hardware revision -> IOSU equivalent flag -> BSP hardware version<br>
−
0x00 -> 0x00000001<br>
+
0x10 -> 0x21100010 -> BSP_HARDWARE_VERSION_LATTE_A11_EV<br>
−
0x10 -> 0x10000001<br>
+
0x10 -> 0x21100020 -> BSP_HARDWARE_VERSION_LATTE_A11_CAT<br>
−
0x11 -> 0x10100001 or 0x10100008 or 0x1010000C<br>
+
0x18 -> 0x21200010 -> BSP_HARDWARE_VERSION_LATTE_A12_EV<br>
−
0x20 -> 0x20000001<br>
+
0x18 -> 0x21200020 -> BSP_HARDWARE_VERSION_LATTE_A12_CAT<br>
−
0x21 -> 0x20100001
+
0x21 -> 0x22100010 -> BSP_HARDWARE_VERSION_LATTE_A2X_EV<br>
 +
0x21 -> 0x22100020 -> BSP_HARDWARE_VERSION_LATTE_A2X_CAT<br>
 +
0x30 -> 0x23100010 -> BSP_HARDWARE_VERSION_LATTE_A3X_EV<br>
 +
0x30 -> 0x23100020 -> BSP_HARDWARE_VERSION_LATTE_A3X_CAT<br>
 +
0x30 -> 0x23100028 -> BSP_HARDWARE_VERSION_LATTE_A3X_CAFE<br>
 +
0x40 -> 0x24100010 -> BSP_HARDWARE_VERSION_LATTE_A4X_EV<br>
 +
0x40 -> 0x24100020 -> BSP_HARDWARE_VERSION_LATTE_A4X_CAT<br>
 +
0x40 -> 0x24100028 -> BSP_HARDWARE_VERSION_LATTE_A4X_CAFE<br>
 +
0x50 -> 0x25100010 -> BSP_HARDWARE_VERSION_LATTE_A5X_EV<br>
 +
0x50 -> 0x25100011 -> BSP_HARDWARE_VERSION_LATTE_A5X_EV_Y<br>
 +
0x50 -> 0x25100020 -> BSP_HARDWARE_VERSION_LATTE_A5X_CAT<br>
 +
0x50 -> 0x25100028 -> BSP_HARDWARE_VERSION_LATTE_A5X_CAFE<br>
 +
0x60 -> 0x26100010 -> BSP_HARDWARE_VERSION_LATTE_B1X_EV<br>
 +
0x60 -> 0x26100011 -> BSP_HARDWARE_VERSION_LATTE_B1X_EV_Y<br>
 +
0x60 -> 0x26100020 -> BSP_HARDWARE_VERSION_LATTE_B1X_CAT<br>
 +
0x60 -> 0x26100028 -> BSP_HARDWARE_VERSION_LATTE_B1X_CAFE<br>
 
{{regdesc
 
{{regdesc
 
|VERHI|Version
 
|VERHI|Version
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|DEBUG|Ask for user input during the IOSU's boot sequence
 
|DEBUG|Ask for user input during the IOSU's boot sequence
 
}}
 
}}
−
  −
{{reg32 | LT_RESETS2 | addr = 0x0d8005e0 | hifields = 1 | lofields = 1 |
  −
|16        |
  −
|?        |
  −
|        ||
  −
|16        |
  −
|?        |
  −
|          |
  −
}}
  −
This register seems to be a mirror of LT_RESETS.
  −
      
{{reg32 | LT_OTPPROT | addr = 0x0d800510 | hifields = 2 | lofields = 1 |
 
{{reg32 | LT_OTPPROT | addr = 0x0d800510 | hifields = 2 | lofields = 1 |
Line 239: Line 262:  
|            |
 
|            |
 
}}
 
}}
−
This register is a bitmask for locking out chunks of the OTP.
+
This register is a bitmask for locking out chunks of the OTP. Each bit clears out 0x20 bytes of the OTP starting from the bottom (bank 7 is 0xF0000000) to the top (bank 0 is 0x0000000F).
 
{{regdesc
 
{{regdesc
 
|BOOT1|Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7
 
|BOOT1|Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7
Hykem
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Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/1646"

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