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Adding AES page
{{Infobox MMIO
| arm = Full
| base = 0x0d020000, 0x0d180000
| len = 0x14
| bits = 32
| ppcirq = None
| latteirq = 2
}}
The Latte's AES Engine encrypts/decrypts 16-byte blocks using AES-128 in Cipher Block Chaining mode.<br>
There are also traces of code inside IOS-CRYPTO that suggest the existence of a second engine named AESS, probably only available in evaluation/debug units.
== Register List ==
{{reglist|AES Engine}}
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
{{rla|0x0d020004|32|AES_SRC|Source memory address}}
{{rla|0x0d020008|32|AES_DEST|Destination memory address}}
{{rla|0x0d02000c|32|AES_KEY|Key FIFO}}
{{rla|0x0d020010|32|AES_IV|IV FIFO}}
|}
<br>
{{reglist|AESS Engine}}
{{rld|0x0d180000|32|AESS_CTRL|AESS Control and Status}}
{{rld|0x0d180004|32|AESS_SRC|Source memory address}}
{{rld|0x0d180008|32|AESS_DEST|Destination memory address}}
{{rld|0x0d18000c|32|AESS_KEY|Key FIFO}}
{{rld|0x0d180010|32|AESS_IV|IV FIFO}}
|}
== Register Details ==
{{reg32 | AES_CTRL | addr = 0x0d020000 | hifields = 6 | lofields = 3 |
|1|1|1|1|1|11|
|R/W|R/W|R/W|R/W|R/W|U|
|EXEC|IRQ|ERR|ENA|DEC|||
|3|1|12|
|U|W|W|
||IV|BLOCKS|
}}
This register controls the state of the AES engine.
{{regdesc
|EXEC|Write 1: initiate AES command<br/>Write 0: reset AES engine<br/>Read: AES engine busy
|IRQ|Set to enable IRQ generation when command is complete
|ERR|If set, AES error occurred (?){{check}}
|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).
|DEC|Set to decrypt, clear to encrypt
|IV|If set, chain from last command (continue CBC mode). If clear, use the supplied IV.
|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.
}}
----
{{regsimple2 | AES_SRC | addr = 0x0d020004 | bits = 32 | split=4 | access = U | accesshi = R/W }}
This register contains the DMA address of the source data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
The engine updates this register as it processes the blocks.
----
{{regsimple2 | AES_DEST | addr = 0x0d020008 | bits = 32 | split=4 | access = U | accesshi = R/W}}
This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
The engine updates this register as it processes the blocks.
----
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).
----
{{regsimple | AES_IV | addr = 0x0d020010 | bits = 32 | access = W }}
This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).
Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.
| arm = Full
| base = 0x0d020000, 0x0d180000
| len = 0x14
| bits = 32
| ppcirq = None
| latteirq = 2
}}
The Latte's AES Engine encrypts/decrypts 16-byte blocks using AES-128 in Cipher Block Chaining mode.<br>
There are also traces of code inside IOS-CRYPTO that suggest the existence of a second engine named AESS, probably only available in evaluation/debug units.
== Register List ==
{{reglist|AES Engine}}
{{rla|0x0d020000|32|AES_CTRL|AES Control and Status}}
{{rla|0x0d020004|32|AES_SRC|Source memory address}}
{{rla|0x0d020008|32|AES_DEST|Destination memory address}}
{{rla|0x0d02000c|32|AES_KEY|Key FIFO}}
{{rla|0x0d020010|32|AES_IV|IV FIFO}}
|}
<br>
{{reglist|AESS Engine}}
{{rld|0x0d180000|32|AESS_CTRL|AESS Control and Status}}
{{rld|0x0d180004|32|AESS_SRC|Source memory address}}
{{rld|0x0d180008|32|AESS_DEST|Destination memory address}}
{{rld|0x0d18000c|32|AESS_KEY|Key FIFO}}
{{rld|0x0d180010|32|AESS_IV|IV FIFO}}
|}
== Register Details ==
{{reg32 | AES_CTRL | addr = 0x0d020000 | hifields = 6 | lofields = 3 |
|1|1|1|1|1|11|
|R/W|R/W|R/W|R/W|R/W|U|
|EXEC|IRQ|ERR|ENA|DEC|||
|3|1|12|
|U|W|W|
||IV|BLOCKS|
}}
This register controls the state of the AES engine.
{{regdesc
|EXEC|Write 1: initiate AES command<br/>Write 0: reset AES engine<br/>Read: AES engine busy
|IRQ|Set to enable IRQ generation when command is complete
|ERR|If set, AES error occurred (?){{check}}
|ENA|Enable en/decryption. If clear, the data is copied straight from source to destination without change (useful as a DMA copy engine?).
|DEC|Set to decrypt, clear to encrypt
|IV|If set, chain from last command (continue CBC mode). If clear, use the supplied IV.
|DATALEN|Number of 16-byte blocks to process, minus one. 0 means one block.
}}
----
{{regsimple2 | AES_SRC | addr = 0x0d020004 | bits = 32 | split=4 | access = U | accesshi = R/W }}
This register contains the DMA address of the source data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
The engine updates this register as it processes the blocks.
----
{{regsimple2 | AES_DEST | addr = 0x0d020008 | bits = 32 | split=4 | access = U | accesshi = R/W}}
This register contains the DMA address of the destination data. The same buffer can be used for source and destination. The address must be 16-byte aligned.
The engine updates this register as it processes the blocks.
----
{{regsimple | AES_KEY | addr = 0x0d02000c | bits = 32 | access = W }}
This register implements a FIFO that accepts the AES key. A sequence of four 32-bit writes will set the AES key (starting with the leftmost 32-bit word).
----
{{regsimple | AES_IV | addr = 0x0d020010 | bits = 32 | access = W }}
This register implements a FIFO that accepts the AES IV. A sequence of four 32-bit writes will set the AES IV (starting with the leftmost 32-bit word).
Clear the IV bit in the [[#AES_CTRL|AES_CTRL]] register to restart the CBC encryption using this IV instead of using the last encrypted block.