In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

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Hardware/Latte registers (view source)

Revision as of 21:50, 13 April 2016

862 bytes added ,  21:50, 13 April 2016
→‎Register list
Line 12: Line 12:  
== Register list ==
 
== Register list ==
 
{{reglist|Latte Registers}}
 
{{reglist|Latte Registers}}
−
{{rld|0x0d800000|32|LT_IPC_PPCMSG|[[Hardware/IPC|IPC]]|drs=4}}
+
{{rld|0x0d800000|32|LT_IPC_PPCMSG_COMPAT|[[Hardware/IPC|IPC (for vWii)]]|drs=4}}
−
{{rld|0x0d800004|32|LT_IPC_PPCCTRL}}
+
{{rld|0x0d800004|32|LT_IPC_PPCCTRL_COMPAT}}
−
{{rld|0x0d800008|32|LT_IPC_ARMMSG}}
+
{{rld|0x0d800008|32|LT_IPC_ARMMSG_COMPAT}}
−
{{rld|0x0d80000c|32|LT_IPC_ARMCTRL}}
+
{{rld|0x0d80000c|32|LT_IPC_ARMCTRL_COMPAT}}
 
{{rld|0x0d800010|32|LT_TIMER|[[Hardware/Starbuck Timer|Starbuck Timer]]|drs=2}}
 
{{rld|0x0d800010|32|LT_TIMER|[[Hardware/Starbuck Timer|Starbuck Timer]]|drs=2}}
 
{{rld|0x0d800014|32|LT_ALARM}}
 
{{rld|0x0d800014|32|LT_ALARM}}
−
{{rld|0x0d800030|32|LT_INTSR_PPC|[[Hardware/Latte_IRQ_Controller|Latte IRQs]]|drs=4}}
+
{{rld|0x0d800030|32|LT_INTSR_PPC_COMPAT|[[Hardware/Latte_IRQ_Controller|Wood IRQs (for vWii)]]|drs=5}}
−
{{rld|0x0d800034|32|LT_INTMR_PPC}}
+
{{rld|0x0d800034|32|LT_INTMR_PPC_COMPAT}}
−
{{rld|0x0d800038|32|LT_INTSR_ARM}}
+
{{rld|0x0d800038|32|LT_INTSR_ARM_COMPAT}}
−
{{rld|0x0d80003c|32|LT_INTMR_ARM}}
+
{{rld|0x0d80003c|32|LT_INTMR_ARM_COMPAT}}
−
{{rld|0x0d800040|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800040|32|LT_INTMR_ARM2x_COMPAT}}
 
{{rld|0x0d800044|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800044|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800048|32|LT_AHB_WDG_STATUS|AHB Watchdog status}}
 
{{rld|0x0d800048|32|LT_AHB_WDG_STATUS|AHB Watchdog status}}
 
{{rld|0x0d80004c|32|LT_AHB_WDG_CONFIG|AHB Watchdog configuration}}
 
{{rld|0x0d80004c|32|LT_AHB_WDG_CONFIG|AHB Watchdog configuration}}
−
{{rld|0x0d800050|32|LT_AHB_DMA_STATUS|AHB DMA status}}
+
{{rld|0x0d800050|32|LT_AHB_DMA_STATUS|AHB DMA transfer status}}
−
{{rld|0x0d800054|32|LT_AHB_CPU_STATUS|AHB CPU status}}
+
{{rld|0x0d800054|32|LT_AHB_CPU_STATUS|AHB CPU transfer status}}
 
{{rld|0x0d800058|32|LT_ERROR|Hardware error code}}
 
{{rld|0x0d800058|32|LT_ERROR|Hardware error code}}
 
{{rld|0x0d80005c|32|LT_ERROR_MASK|Hardware error code mask}}
 
{{rld|0x0d80005c|32|LT_ERROR_MASK|Hardware error code mask}}
Line 53: Line 53:  
{{rld|0x0d8000f8|32|LT_GPIO_INMIR}}
 
{{rld|0x0d8000f8|32|LT_GPIO_INMIR}}
 
{{rld|0x0d8000fc|32|LT_GPIO_OWNER}}
 
{{rld|0x0d8000fc|32|LT_GPIO_OWNER}}
−
{{rld|0x0d800100|32|LT_AHB_UNK1|AHB specific registers|drs=13}}
+
{{rld|0x0d800100|32|LT_AHB_UNK|AHB specific registers|drs=13}}
−
{{rld|0x0d800104|32|LT_AHB_UNK2}}
+
{{rld|0x0d800104|32|LT_AHB_UNK}}
−
{{rld|0x0d800108|32|LT_AHB_UNK3}}
+
{{rld|0x0d800108|32|LT_AHB_UNK}}
−
{{rld|0x0d80010c|32|LT_AHB_UNK4}}
+
{{rld|0x0d80010c|32|LT_AHB_UNK}}
−
{{rld|0x0d800110|32|LT_AHB_UNK5}}
+
{{rld|0x0d800110|32|LT_AHB_UNK}}
−
{{rld|0x0d800114|32|LT_AHB_UNK6}}
+
{{rld|0x0d800114|32|LT_AHB_UNK}}
−
{{rld|0x0d800118|32|LT_AHB_UNK7}}
+
{{rld|0x0d800118|32|LT_AHB_UNK}}
−
{{rld|0x0d80011c|32|LT_AHB_UNK8}}
+
{{rld|0x0d80011c|32|LT_AHB_UNK}}
−
{{rld|0x0d800120|32|LT_AHB_UNK9}}
+
{{rld|0x0d800120|32|LT_AHB_UNK}}
−
{{rld|0x0d800124|32|LT_AHB_UNK10}}
+
{{rld|0x0d800124|32|LT_AHB_UNK}}
−
{{rld|0x0d800130|32|LT_AHB_UNK11}}
+
{{rld|0x0d800130|32|LT_AHB_UNK}}
−
{{rld|0x0d800134|32|LT_AHB_UNK12}}
+
{{rld|0x0d800134|32|LT_AHB_UNK}}
−
{{rld|0x0d800138|32|LT_AHB_UNK13}}
+
{{rld|0x0d800138|32|LT_AHB_UNK}}
−
{{rld|0x0d800140|32|LT_ARB_CFG|Unknown}}
+
{{rld|0x0d800140|32|LT_ARB_CFG|AHB Arbiter configuration}}
−
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface stuff{{check}}}}
+
{{rld|0x0d800180|32|LT_DIFLAGS|Drive interface flags (for vWii)}}
−
{{rld|0x0d800184|32|LT_AHB_RESETS|Unknown}}
+
{{rld|0x0d800184|32|LT_RESETS_AHB|Resets for elements connected to the AHB}}
−
{{rld|0x0d800188|32|LT_COMPAT_UNK1|Unknown}}
+
{{rld|0x0d800188|32|LT_COMPAT_MEMCTRL_WORKAROUND|Unknown}}
−
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 {{check}}}}
+
{{rla|0x0d80018c|32|LT_BOOT0|Maps boot0 and controls a few other things}}
 
{{rld|0x0d800190|32|LT_CLOCKINFO|Clock information}}
 
{{rld|0x0d800190|32|LT_CLOCKINFO|Clock information}}
−
{{rld|0x0d800194|32|LT_RESETS|System resets {{check}}}}
+
{{rld|0x0d800194|32|LT_RESETS_COMPAT|System resets (for Wood based hardware)}}
−
{{rld|0x0d800198|32|LT_CLOCKGATE1|Interfaces' clock gate}}
+
{{rld|0x0d800198|32|LT_CLOCKGATE_COMPAT|Interfaces' clock gate (for Wood based hardware)}}
−
{{rld|0x0d8001a8|32|LT_SATAPLL_UNK1|Unknown}}
+
{{rld|0x0d8001a8|32|LT_SATA_UNK|Unknown}}
−
{{rld|0x0d8001c8|32|LT_SATAPLL_UNK2|Unknown}}
+
{{rld|0x0d8001c8|32|LT_SATA_UNK|Unknown}}
−
{{rld|0x0d8001cc|32|LT_SATAPLL_UNK3|Unknown}}
+
{{rld|0x0d8001cc|32|LT_SATA_UNK|Unknown}}
−
{{rld|0x0d8001d0|32|LT_SATAPLL_UNK4|Unknown}}
+
{{rld|0x0d8001d0|32|LT_SATA_UNK|Unknown}}
 
{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8001d8|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8001dc|32|LT_IOPOWER|Subsystems' power state}}
 
{{rld|0x0d8001dc|32|LT_IOPOWER|Subsystems' power state}}
−
{{rld|0x0d8001e0|32|LT_IOSTRENGTH_CTRL0|Subsystems' power strength}}
+
{{rld|0x0d8001e0|32|LT_IOSTRENGTH_CTRL0|Subsystems' power strength control}}
−
{{rld|0x0d8001e4|32|LT_IOSTRENGTH_CTRL1|Subsystems' power strength}}
+
{{rld|0x0d8001e4|32|LT_IOSTRENGTH_CTRL1|Subsystems' power strength control}}
−
{{rld|0x0d8001e8|32|LT_ACRCLK_STRENGTH_CTRL|ACR clock's power strength}}
+
{{rld|0x0d8001e8|32|LT_ACRCLK_STRENGTH_CTRL|ACR chip's clock power strength}}
 
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001ec|32|LT_OTPCMD|[[Hardware/OTP|OTP]]|drs=2}}
 
{{rld|0x0d8001f0|32|LT_OTPDATA}}
 
{{rld|0x0d8001f0|32|LT_OTPDATA}}
 
{{rld|0x0d800204|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800204|32|UNKNOWN|Unknown}}
−
{{rla|0x0d800214|32|LT_ASICREV_ACR|ACR chip revision ID (Hollywood)}}
+
{{rla|0x0d800214|32|LT_ASICREV_ACR|ACR chip's revision ID (Hollywood/Bollywood)}}
 +
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800258|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800258|32|UNKNOWN|Unknown}}
−
{{rld|0x0d800400|32|LT_IPC_PPC0_PPCMSG|[[Hardware/IPC|IPC]] (per-core)|drs=12}}
+
{{rld|0x0d800400|32|LT_IPC_PPC0_PPCMSG|[[Hardware/IPC|IPC]] (per-core, for Latte)|drs=12}}
 
{{rld|0x0d800404|32|LT_IPC_PPC0_PPCCTRL}}
 
{{rld|0x0d800404|32|LT_IPC_PPC0_PPCCTRL}}
 
{{rld|0x0d800408|32|LT_IPC_PPC0_ARMMSG}}
 
{{rld|0x0d800408|32|LT_IPC_PPC0_ARMMSG}}
Line 102: Line 103:  
{{rld|0x0d800428|32|LT_IPC_PPC2_ARMMSG}}
 
{{rld|0x0d800428|32|LT_IPC_PPC2_ARMMSG}}
 
{{rld|0x0d80042c|32|LT_IPC_PPC2_ARMCTRL}}
 
{{rld|0x0d80042c|32|LT_IPC_PPC2_ARMCTRL}}
−
{{rld|0x0d800440|32|LT_INTSR_AHBALL_PPC0|[[Hardware/Latte_IRQ_Controller|Latte IRQs]] (per-core)|drs=12}}
+
{{rld|0x0d800440|32|LT_INTSR_AHBALL_PPC0|[[Hardware/Latte_IRQ_Controller|Latte IRQs]] (per-core, for Latte)|drs=18}}
 
{{rld|0x0d800444|32|LT_INTSR_AHBLT_PPC0}}
 
{{rld|0x0d800444|32|LT_INTSR_AHBLT_PPC0}}
 
{{rld|0x0d800448|32|LT_INTMR_AHBALL_PPC0}}
 
{{rld|0x0d800448|32|LT_INTMR_AHBALL_PPC0}}
Line 114: Line 115:  
{{rld|0x0d800468|32|LT_INTMR_AHBALL_PPC2}}
 
{{rld|0x0d800468|32|LT_INTMR_AHBALL_PPC2}}
 
{{rld|0x0d80046c|32|LT_INTMR_AHBLT_PPC2}}
 
{{rld|0x0d80046c|32|LT_INTMR_AHBLT_PPC2}}
−
{{rld|0x0d800470|32|LT_INTSR_ARM2|Unknown duplicate}}
+
{{rld|0x0d800470|32|LT_INTSR_AHBALL_ARM}}
−
{{rld|0x0d800474|32|LT_GPIO_INTFLAG2|Unknown duplicate}}
+
{{rld|0x0d800474|32|LT_INTSR_AHBLT_ARM}}
−
{{rld|0x0d800478|32|LT_INTMR_ARM2|Unknown duplicate}}
+
{{rld|0x0d800478|32|LT_INTMR_AHBALL_ARM}}
−
{{rld|0x0d80047c|32|LT_GPIO_INTMASK2|Unknown duplicate}}
+
{{rld|0x0d80047c|32|LT_INTMR_AHBLT_ARM}}
−
{{rld|0x0d800480|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800480|32|LT_INTMR_AHBALL_ARM2x}}
−
{{rld|0x0d800484|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800484|32|LT_INTMR_AHBLT_ARM2x}}
 
{{rld|0x0d8004a0|32|LT_AHB2_WDG_STATUS|AHB2 Watchdog status}}
 
{{rld|0x0d8004a0|32|LT_AHB2_WDG_STATUS|AHB2 Watchdog status}}
−
{{rld|0x0d8004a4|32|LT_AHB2_DMA_STATUS|AHB2 DMA status}}
+
{{rld|0x0d8004a4|32|LT_AHB2_DMA_STATUS|AHB2 DMA transfer status}}
−
{{rld|0x0d8004a8|32|LT_AHB2_CPU_STATUS|AHB2 CPU status}}
+
{{rld|0x0d8004a8|32|LT_AHB2_CPU_STATUS|AHB2 CPU transfer status}}
 +
{{rld|0x0d8004c8|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004cc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004d0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004d4|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004dc|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004e0|32|UNKNOWN|Unknown}}
 +
{{rld|0x0d8004e4|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800500|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800504|32|UNKNOWN|Unknown}}
 
{{rla|0x0d800510|32|LT_OTPPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each)}}
 
{{rla|0x0d800510|32|LT_OTPPROT|Bitmask used to lock out chunks of OTP (0x20 bytes each)}}
 
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for vWii mode}}
 
{{rld|0x0d800514|32|LT_SYSPROT|Hardware sandbox for vWii mode}}
−
{{rld|0x0d800520|32|LT_GPIOE_OUT2|[[Hardware/Latte GPIOs|Latte GPIOs (mirror?)]]|drs=16}}
+
{{rld|0x0d800520|32|LT_GPIOE2_OUT|[[Hardware/Latte GPIOs|Latte GPIOs (second line)]]|drs=16}}
−
{{rld|0x0d800524|32|LT_GPIOE_DIR2}}
+
{{rld|0x0d800524|32|LT_GPIOE2_DIR}}
−
{{rld|0x0d800528|32|LT_GPIOE_IN2}}
+
{{rld|0x0d800528|32|LT_GPIOE2_IN}}
−
{{rld|0x0d80052c|32|LT_GPIOE_INTLVL2}}
+
{{rld|0x0d80052c|32|LT_GPIOE2_INTLVL}}
−
{{rld|0x0d800530|32|LT_GPIOE_INTFLAG2}}
+
{{rld|0x0d800530|32|LT_GPIOE2_INTFLAG}}
−
{{rld|0x0d800534|32|LT_GPIOE_INTMASK2}}
+
{{rld|0x0d800534|32|LT_GPIOE2_INTMASK}}
−
{{rld|0x0d800538|32|LT_GPIOE_INMIR2}}
+
{{rld|0x0d800538|32|LT_GPIOE2_INMIR}}
−
{{rld|0x0d80053c|32|LT_GPIO_ENABLE2}}
+
{{rld|0x0d80053c|32|LT_GPIO2_ENABLE}}
−
{{rld|0x0d800540|32|LT_GPIO_OUT2}}
+
{{rld|0x0d800540|32|LT_GPIO2_OUT}}
−
{{rld|0x0d800544|32|LT_GPIO_DIR2}}
+
{{rld|0x0d800544|32|LT_GPIO2_DIR}}
−
{{rld|0x0d800548|32|LT_GPIO_IN2}}
+
{{rld|0x0d800548|32|LT_GPIO2_IN}}
−
{{rld|0x0d80054c|32|LT_GPIO_INTLVL2}}
+
{{rld|0x0d80054c|32|LT_GPIO2_INTLVL}}
−
{{rld|0x0d800550|32|LT_GPIO_INTFLAG2}}
+
{{rld|0x0d800550|32|LT_GPIO2_INTFLAG}}
−
{{rld|0x0d800554|32|LT_GPIO_INTMASK2}}
+
{{rld|0x0d800554|32|LT_GPIO2_INTMASK}}
−
{{rld|0x0d800558|32|LT_GPIO_INMIR2}}
+
{{rld|0x0d800558|32|LT_GPIO2_INMIR}}
−
{{rld|0x0d80055c|32|LT_GPIO_OWNER2}}
+
{{rld|0x0d80055c|32|LT_GPIO2_OWNER}}
−
{{rld|0x0d800570|32|LT_I2C_UNK1|I2C specific registers|drs=6}}
+
{{rld|0x0d800570|32|LT_I2C_CLOCK|I2C specific registers|drs=6}}
 
{{rld|0x0d800574|32|LT_I2C_INOUT_DATA}}
 
{{rld|0x0d800574|32|LT_I2C_INOUT_DATA}}
 
{{rld|0x0d800578|32|LT_I2C_INOUT_CTRL}}
 
{{rld|0x0d800578|32|LT_I2C_INOUT_CTRL}}
Line 151: Line 159:  
{{rla|0x0d8005a0|32|LT_ASICREV_CCR|CCR chip revision ID (Latte)}}
 
{{rla|0x0d8005a0|32|LT_ASICREV_CCR|CCR chip revision ID (Latte)}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|DEBUG mode flags}}
−
{{rld|0x0d8005b0|32|LT_COMPAT_MEMCTRL|Compat mode registers|drs=5}}
+
{{rld|0x0d8005b0|32|LT_COMPAT_MEMCTRL_STATE|Compat memory control mode (for vWii)}}
−
{{rld|0x0d8005b4|32|LT_COMPAT_AHB}}
+
{{rld|0x0d8005b4|32|LT_COMPAT_AHB_STATE|Compat AHB mode (for vWii)}}
−
{{rld|0x0d8005b8|32|LT_COMPAT_STEREO_OUT_SELECT}}
+
{{rld|0x0d8005b8|32|LT_COMPAT_STEREO_OUT_SELECT|Stereo configuration (for vWii)}}
−
{{rld|0x0d8005bc|32|LT_IOP2X}}
+
{{rld|0x0d8005bc|32|LT_IOP2X|Unknown}}
−
{{rld|0x0d8005c0|32|LT_COMPAT_UNK2}}
+
{{rld|0x0d8005c0|32|UNKNOWN|Unknown}}
−
{{rld|0x0d8005c8|32|LT_IOSTRENGTH_CTRL2|Subsystems' power strength}}
+
{{rld|0x0d8005c8|32|LT_IOSTRENGTH_CTRL2|Subsystems' power strength control}}
 
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
 
{{rld|0x0d8005cc|32|UNKNOWN|Unknown}}
−
{{rld|0x0d8005e0|32|LT_RESETS2|System resets {{check}}}}
+
{{rld|0x0d8005e0|32|LT_RESETS|System resets (for Latte based hardware)}}
−
{{rld|0x0d8005e4|32|LT_AHMN_RESETS|Unknown}}
+
{{rld|0x0d8005e4|32|LT_RESETS_AHMN|Resets for elements connected to the AHB XN unit}}
−
{{rld|0x0d8005e8|32|LT_CLOCKGATE2|Unknown}}
+
{{rld|0x0d8005e8|32|LT_CLOCKGATE|Interfaces' clock gate (for Latte based hardware)}}
−
{{rld|0x0d8005ec|32|LT_SYSPLL_UNK|SYSPLL registers|drs=3}}
+
{{rld|0x0d8005ec|32|LT_SYSPLL_CFG|System PLL configuration}}
−
{{rld|0x0d800620|32|LT_SYSPLL_OFFSET}}
+
{{rld|0x0d800620|32|LT_ABIF_CPLTL_OFFSET|ASIC BIF (bus interface) Cpl Tl read/write offset}}
−
{{rld|0x0d800624|32|LT_SYSPLL_DATA}}
+
{{rld|0x0d800624|32|LT_ABIF_CPLTL_DATA|ASIC BIF (bus interface) Cpl Tl read/write data}}
 
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
−
{{rld|0x0d800640|32|LT_60XE_DATA_STREAMING|Unknown}}
+
{{rld|0x0d800640|32|LT_60XE_CFG|60Xe data bus configuration}}
 
{{rld|0x0d800660|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800660|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800640|32|UNKNOWN|Unknown}}
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Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/1787"

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