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Created page with "{{Infobox MMIO | ppc = None | arm = Full | base = 0x0d8b0800 | len = 0x800 | bits = 32 | ppcirq = ??? | latteirq = ??? }} Similarly to the [[Hardware/Memory_Controller|memory..."
{{Infobox MMIO
| ppc = None
| arm = Full
| base = 0x0d8b0800
| len = 0x800
| bits = 32
| ppcirq = ???
| latteirq = ???
}}
Similarly to the [[Hardware/Memory_Controller|memory controller]] block connected to the AHB, the Latte hardware implements a customized XN (eXecute Never) controller to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).<br>
This controller is named AHMN (AHB memory XN?) by the IOSU.
== Register List ==
{{reglist|XN Controller}}
{{rld|0x0d8b0800|32|AHMN_MEM0_CONFIG|AHMN configuration for MEM0 protection}}
{{rld|0x0d8b0804|32|AHMN_MEM1_CONFIG|AHMN configuration for MEM1 protection}}
{{rld|0x0d8b0808|32|AHMN_MEM2_CONFIG|AHMN configuration for MEM2 protection}}
{{rld|0x0d8b080c|32|AHMN_RDBI_MASK|AHMN read buffer invalidate mask}}
{{rld|0x0d8b0820|32|AHMN_ERROR_MASK|AHMN protection violation's error mask}}
{{rld|0x0d8b0824|32|AHMN_ERROR|AHMN protection violation's error state}}
{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}
{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}
{{rld|0x0d8b0850|32|AHMN_TRANSFER_STATE|AHMN read/write transfer state}}
{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}
{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}
{{rld|0x0d8b0a00...0x0d8b0c00|32|AHMN_MEM1|Each register represents one block of MEM1 memory (block size depends on the AHMN configuration for MEM1)}}
{{rld|0x0d8b0c00...0x0d8b1000|32|AHMN_MEM2|Each register represents one block of MEM2 memory (block size depends on the AHMN configuration for MEM2)}}
|}
== Register Details ==
| ppc = None
| arm = Full
| base = 0x0d8b0800
| len = 0x800
| bits = 32
| ppcirq = ???
| latteirq = ???
}}
Similarly to the [[Hardware/Memory_Controller|memory controller]] block connected to the AHB, the Latte hardware implements a customized XN (eXecute Never) controller to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).<br>
This controller is named AHMN (AHB memory XN?) by the IOSU.
== Register List ==
{{reglist|XN Controller}}
{{rld|0x0d8b0800|32|AHMN_MEM0_CONFIG|AHMN configuration for MEM0 protection}}
{{rld|0x0d8b0804|32|AHMN_MEM1_CONFIG|AHMN configuration for MEM1 protection}}
{{rld|0x0d8b0808|32|AHMN_MEM2_CONFIG|AHMN configuration for MEM2 protection}}
{{rld|0x0d8b080c|32|AHMN_RDBI_MASK|AHMN read buffer invalidate mask}}
{{rld|0x0d8b0820|32|AHMN_ERROR_MASK|AHMN protection violation's error mask}}
{{rld|0x0d8b0824|32|AHMN_ERROR|AHMN protection violation's error state}}
{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}
{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}
{{rld|0x0d8b0850|32|AHMN_TRANSFER_STATE|AHMN read/write transfer state}}
{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}
{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}
{{rld|0x0d8b0a00...0x0d8b0c00|32|AHMN_MEM1|Each register represents one block of MEM1 memory (block size depends on the AHMN configuration for MEM1)}}
{{rld|0x0d8b0c00...0x0d8b1000|32|AHMN_MEM2|Each register represents one block of MEM2 memory (block size depends on the AHMN configuration for MEM2)}}
|}
== Register Details ==