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Line 9:
Line 9:
<br>
| arm = Full
| arm = Full
| base = 0x0d806000
| base = 0x0d806000
−| len = 0x100
+| len = 0x400
| bits = 32
| bits = 32
| ppcirq = ???
| ppcirq = ???
Line 17:
Line 17:
== Register List ==
== Register List ==
{{reglist|Drive Interface}}
{{reglist|Drive Interface}}
−{{rld|0x0d806000|32|DI2SATA_SR_IDX|DI status register}}
+{{rld|0x0d806000|32|DI2SATA_SR|DI status register}}
{{rld|0x0d806004|32|DI2SATA_CVR|DI cover register (status2)}}
{{rld|0x0d806004|32|DI2SATA_CVR|DI cover register (status2)}}
{{rld|0x0d806008|32|DI2SATA_CMDBUF0|DI command buffer 0}}
{{rld|0x0d806008|32|DI2SATA_CMDBUF0|DI command buffer 0}}
Line 26:
Line 26:
{{rld|0x0d80601c|32|DI2SATA_CR|Unknown}}
{{rld|0x0d80601c|32|DI2SATA_CR|Unknown}}
{{rld|0x0d806020|32|DI2SATA_IMMBUF|DI immediate data buffer}}
{{rld|0x0d806020|32|DI2SATA_IMMBUF|DI immediate data buffer}}
−{{rld|0x0d806024|32|DI2SATA_CFG|DI configuration register}}
+{{rld|0x0d806024|32|DI2SATA_CONFIG|DI configuration register}}
−{{rld|0x0d806028|32|DI2SATA_COMPAT_STATE|DI compat mode state}}
+{{rld|0x0d806028|32|DI2SATA_COMPAT|DI compat mode}}
|}
|}
== Register Details ==
== Register Details ==
+<br>
<br>
<br>
= Serial Interface =
= Serial Interface =
Line 40:
Line 41:
| arm = Full
| arm = Full
| base = 0x0d806400
| base = 0x0d806400
−| len = 0x100
+| len = 0x400
| bits = 32
| bits = 32
| ppcirq = ???
| ppcirq = ???
Line 50:
Line 51:
== Register Details ==
== Register Details ==
+<br>
<br>
<br>
= External Interface =
= External Interface =
−{{Infobox MMIO
{{Infobox MMIO
| title = External Interface
| title = External Interface
Line 58:
Line 59:
| arm = Full
| arm = Full
| base = 0x0d806800
| base = 0x0d806800
−| len = 0x100
+| len = 0x400
| bits = 32
| bits = 32
| ppcirq = ???
| ppcirq = ???
| latteirq = ???
| latteirq = ???
}}
}}
+
+For compatibility purposes, the Wii U implements the External Interface similarly to the GameCube and the Wii.
+On a regular retail Wii U, the [[Hardware/RTC|RTC]] is the only device registered on the EXI bus (channel 0, device 1). An additional device called [[Hardware/NESCAFE|NESCAFE]] (part of the debug [[Hardware/CORTADO|CORTADO]] package) was presumably used in the past for debugging purposes and used to sit on channel 0 as device 2.
+
+This bus is accessible externally via the following test points:
+* TP101 - CLK
+* TP176 - MISO (Device out, Wii U in)
+* Test point between TP100 and TP176 - MOSI (Device in, Wii U out)
== Register List ==
== Register List ==
+{{reglist|EXI Interface}}
+{{rld|0x0d806800|32|EXI0_CSR|EXI Channel 0 Parameter Register}}
+{{rld|0x0d806804|32|EXI0_MAR|EXI Channel 0 DMA Start Address}}
+{{rld|0x0d806808|32|EXI0_LENGTH|EXI Channel 0 DMA Transfer Length}}
+{{rld|0x0d80680c|32|EXI0_CR|EXI Channel 0 Control Register}}
+{{rld|0x0d806810|32|EXI0_DATA|EXI Channel 0 Immediate Data}}
+{{rld|0x0d806814|32|EXI1_CSR|EXI Channel 1 Parameter Register}}
+{{rld|0x0d806818|32|EXI1_MAR|EXI Channel 1 DMA Start Address}}
+{{rld|0x0d80681c|32|EXI1_LENGTH|EXI Channel 1 DMA Transfer Length}}
+{{rld|0x0d806820|32|EXI1_CR|EXI Channel 1 Control Register}}
+{{rld|0x0d806824|32|EXI1_DATA|EXI Channel 1 Immediate Data}}
+{{rld|0x0d806828|32|EXI2_CSR|EXI Channel 2 Parameter Register}}
+{{rld|0x0d80682c|32|EXI2_MAR|EXI Channel 2 DMA Start Address}}
+{{rld|0x0d806830|32|EXI2_LENGTH|EXI Channel 2 DMA Transfer Length}}
+{{rld|0x0d806834|32|EXI2_CR|EXI Channel 2 Control Register}}
+{{rld|0x0d806838|32|EXI2_DATA|EXI Channel 2 Immediate Data}}
+|}
== Register Details ==
== Register Details ==
+{{regsimple | EXIx_CR | addr = 0x0d80680c/0x0d806820/0x0d806834 | bits = 32 | access = W }}
+{{regsimple | EXIx_DATA | addr = 0x0d806810/0x0d806824/0x0d806838 | bits = 32 | access = R/W }}
+When IOSU sends data to the device, it:
+* Writes the data into EXI_DATA
+* Writes 0x35 into EXI_CR
+* Waits for [[Hardware/Latte_IRQ_Controller|IRQ]] #20
+
+When IOSU reads data from the device, it:
+* Writes 0x31 into EXI_CR
+* Waits for [[Hardware/Latte_IRQ_Controller|IRQ]] #20
+* Reads the data from EXI_DATA
−= Audio Interface =
= Audio Interface =
Line 76:
Line 112:
| arm = Full
| arm = Full
| base = 0x0d806c00
| base = 0x0d806c00
−| len = 0x100
+| len = 0x400
| bits = 32
| bits = 32
| ppcirq = ???
| ppcirq = ???