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The Latte chipset includes two groups of general purpose I/O lines with interrupt capability. Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.
+
The Latte chipset includes two groups of general purpose I/O lines with interrupt capability: one common to Wood and Latte hardware (ALL) and another exclusively available to Latte (LT). Four sets of registers are provided (two for each group), and the Espresso only has access to two sets. These sets access a configurable subset of the IO pins, which the Starbuck can select.
    
== Pin connections ==
 
== Pin connections ==
Line 21: Line 21:  
! Description
 
! Description
 
|-
 
|-
| 0 || 1 || IN || RTCSysInt || Power button input.
+
| 0 || ALL || IN || RTCSysInt || Power button input.
 
|-
 
|-
| 0 || 2 || OUT || FanSpeed || Fan speed.
+
| 0 || LT || OUT || FanSpeed || Fan speed.
 
|-
 
|-
| 0 || 1 || I/O || ToucanSelect || "Toucan" select (devkit only).
+
| 0 || ALL || I/O || ToucanSelect || "Toucan" select (devkit only).
 
|-
 
|-
| 1 || 1 || OUT || DWiFiMode || DWiFi mode.
+
| 1 || ALL || OUT || DWiFiMode || DWiFi mode.
 
|-
 
|-
| 1 || 2 || IN || SMCI2CClock || SMC (surface mounted components) I²C Clock.
+
| 1 || LT || IN || SMCI2CClock || SMC (surface mounted components) I²C Clock.
 
|-
 
|-
| 2 || 1 || OUT || FanPower || Fan power, active high.
+
| 2 || ALL || OUT || FanPower || Fan power, active high.
 
|-
 
|-
| 2 || 2 || IN || SMCI2CData || SMC (surface mounted components) I²C Data.
+
| 2 || LT || IN || SMCI2CData || SMC (surface mounted components) I²C Data.
 
|-
 
|-
| 3 || 1 || OUT || DCDCPwrCnt || DC/DC converter power (group 1), active high.
+
| 3 || ALL || OUT || DCDCPwrCnt || DC/DC converter power, active high.
 
|-
 
|-
| 3 || 2 || OUT || DCDCPwrCnt2 || DC/DC converter power (group 2), active high.
+
| 3 || LT || OUT || DCDCPwrCnt2 || DC/DC converter power, active high.
 
|-
 
|-
| 3 || 1 || OUT || CCRIO3 || Unknown (duplicate?)
+
| 3 || ALL || OUT || CCRIO3 || Unknown (duplicate?)
 
|-
 
|-
| 4 || 1 || UNK || UNKNOWN || Unknown.
+
| 4 || ALL || UNK || UNKNOWN || Unknown.
 
|-
 
|-
| 4 || 2 || IN || AVInterrupt || A/V encoder interrupt (from Espresso).
+
| 4 || LT || IN || AVInterrupt || A/V encoder interrupt (from Espresso).
 
|-
 
|-
| 5 || 1 || OUT || ESP10WorkAround || Unknown.
+
| 5 || ALL || OUT || ESP10WorkAround || Unknown.
 
|-
 
|-
| 5 || 2 || OUT || CCRIO12 || Unknown.
+
| 5 || LT || OUT || CCRIO12 || Unknown.
 
|-
 
|-
| 6 || 1 || UNK || UNKNOWN || Unknown.
+
| 6 || ALL || UNK || UNKNOWN || Unknown.
 
|-
 
|-
| 6 || 2 || OUT || AVReset || A/V encoder reset (from Espresso).
+
| 6 || LT || OUT || AVReset || A/V encoder reset (from Espresso).
 
|-
 
|-
| 7 || 1 || UNK || UNKNOWN || Unknown.
+
| 7 || ALL || UNK || UNKNOWN || Unknown.
 
|-
 
|-
| 8 || 1 || OUT || PADPD || Gamepad power state.
+
| 8 || ALL || OUT || PADPD || Gamepad power state.
 
|-
 
|-
| 9 || 1 || UNK || UNKNOWN  || Unknown.
+
| 9 || ALL || UNK || UNKNOWN  || Unknown.
 
|-
 
|-
| 10 || 1 || OUT || EEPROM_CS || SEEPROM Chip Select.
+
| 10 || ALL || OUT || EEPROM_CS || SEEPROM Chip Select.
 
|-
 
|-
| 11 || 1 || OUT || EEPROM_SK || SEEPROM Clock.
+
| 11 || ALL || OUT || EEPROM_SK || SEEPROM Clock.
 
|-
 
|-
| 12 || 1 || OUT || EEPROM_DO || Data to SEEPROM.
+
| 12 || ALL || OUT || EEPROM_DO || Data to SEEPROM.
 
|-
 
|-
| 13 || 1 || IN || EEPROM_DI || Data from SEEPROM.
+
| 13 || ALL || IN || EEPROM_DI || Data from SEEPROM.
 
|-
 
|-
| 14 || 1 || OUT || AV0I2CClock || A/V Encoder (#0) I²C Clock.
+
| 14 || ALL || OUT || AV0I2CClock || A/V Encoder (#0) I²C Clock.
 
|-
 
|-
| 15 || 1 || OUT || AV0I2CData || A/V Encoder (#0) I²C Data.
+
| 15 || ALL || OUT || AV0I2CData || A/V Encoder (#0) I²C Data.
 
|-
 
|-
| 16 || 1 || I/O || NDEV_LED || Development unit's LED (devkit only).
+
| 16 || ALL || I/O || NDEV_LED || Development unit's LED (devkit only).
 
|-
 
|-
| 16 || 1 || OUT || DEBUG0 || Debug Testpoint.
+
| 16 || ALL || OUT || DEBUG0 || Debug Testpoint.
 
|-
 
|-
| 17 || 1 || OUT || DEBUG1 || Debug Testpoint.
+
| 17 || ALL || OUT || DEBUG1 || Debug Testpoint.
 
|-
 
|-
| 18 || 1 || OUT || DEBUG2 || Debug Testpoint.
+
| 18 || ALL || OUT || DEBUG2 || Debug Testpoint.
 
|-
 
|-
| 19 || 1 || OUT || DEBUG3 || Debug Testpoint.
+
| 19 || ALL || OUT || DEBUG3 || Debug Testpoint.
 
|-
 
|-
| 20 || 1 || OUT || DEBUG4 || Debug Testpoint.
+
| 20 || ALL || OUT || DEBUG4 || Debug Testpoint.
 
|-
 
|-
| 21 || 1 || OUT || DEBUG5 || Debug Testpoint.
+
| 21 || ALL || OUT || DEBUG5 || Debug Testpoint.
 
|-
 
|-
| 22 || 1 || OUT || DEBUG6 || Debug Testpoint.
+
| 22 || ALL || OUT || DEBUG6 || Debug Testpoint.
 
|-
 
|-
| 23 || 1 || OUT || DEBUG7 || Debug Testpoint.
+
| 23 || ALL || OUT || DEBUG7 || Debug Testpoint.
 
|-
 
|-
| 24 || 1 || OUT || AV1I2CClock || A/V Encoder (#1) I²C Clock.
+
| 24 || ALL || OUT || AV1I2CClock || A/V Encoder (#1) I²C Clock.
 
|-
 
|-
| 25 || 1 || OUT || AV1I2CData || A/V Encoder (#1) I²C Data.
+
| 25 || ALL || OUT || AV1I2CData || A/V Encoder (#1) I²C Data.
 
|-
 
|-
| 26 || 1 || OUT || MuteLamp || Unknown.
+
| 26 || ALL || OUT || MuteLamp || Unknown.
 
|-
 
|-
| 27 || 1 || OUT || BlueToothMode || BlueTooth mode.
+
| 27 || ALL || OUT || BlueToothMode || BlueTooth mode.
 
|-
 
|-
| 28 || 1 || OUT || CCRHReset || CCR (constant current regulator?) hard reset.
+
| 28 || ALL || OUT || CCRHReset || CCR (constant current regulator?) hard reset.
 
|-
 
|-
| 29 || 1 || OUT || WiFiMode || WiFi mode.
+
| 29 || ALL || OUT || WiFiMode || WiFi mode.
 
|-
 
|-
| 30 || 1 || OUT || SDC0S0Power || SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD card.
+
| 30 || ALL || OUT || SDC0S0Power || SD card (slot 0) power. Driven low before boot0 attempts to read a signed boot1 image from the SD card.
 
|}
 
|}
    
== Register list ==
 
== Register list ==
{{reglist|Latte GPIOs (group 1)}}
+
{{reglist|Wood and Latte GPIOs (ALL)}}
{{rla|0x0d8000c0|32|LT_GPIOE_OUT|GPIO Outputs (Espresso access)}}
+
{{rla|0x0d8000c0|32|HW_GPIOB_OUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d8000c4|32|LT_GPIOE_DIR|GPIO Direction (Espresso access)}}
+
{{rla|0x0d8000c4|32|HW_GPIOB_DIR|GPIO Direction (Espresso access)}}
{{rla|0x0d8000c8|32|LT_GPIOE_IN|GPIO Inputs (Espresso access)}}
+
{{rla|0x0d8000c8|32|HW_GPIOB_IN|GPIO Inputs (Espresso access)}}
{{rla|0x0d8000cc|32|LT_GPIOE_INTLVL|GPIO Interrupt Levels (Espresso access)}}
+
{{rla|0x0d8000cc|32|HW_GPIOB_INTLVL|GPIO Interrupt Levels (Espresso access)}}
{{rla|0x0d8000d0|32|LT_GPIOE_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
+
{{rla|0x0d8000d0|32|HW_GPIOB_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d8000d4|32|LT_GPIOE_INTMASK|GPIO Interrupt Masks (Espresso access)}}
+
{{rla|0x0d8000d4|32|HW_GPIOB_INTMASK|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d8000d8|32|LT_GPIOE_INMIR|GPIO Input Mirror (Espresso access)}}
+
{{rla|0x0d8000d8|32|HW_GPIOB_STRAPS|GPIO Straps (Espresso access)}}
{{rla|0x0d8000dc|32|LT_GPIO_ENABLE|GPIO Enable (Starbuck only)}}
+
{{rla|0x0d8000dc|32|HW_GPIO_ENABLE|GPIO Enable (Starbuck only)}}
{{rla|0x0d8000e0|32|LT_GPIO_OUT|GPIO Outputs (Starbuck only)}}
+
{{rla|0x0d8000e0|32|HW_GPIO_OUT|GPIO Outputs (Starbuck only)}}
{{rla|0x0d8000e4|32|LT_GPIO_DIR|GPIO Direction (Starbuck only)}}
+
{{rla|0x0d8000e4|32|HW_GPIO_DIR|GPIO Direction (Starbuck only)}}
{{rla|0x0d8000e8|32|LT_GPIO_IN|GPIO Inputs (Starbuck only)}}
+
{{rla|0x0d8000e8|32|HW_GPIO_IN|GPIO Inputs (Starbuck only)}}
{{rla|0x0d8000ec|32|LT_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
+
{{rla|0x0d8000ec|32|HW_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
{{rla|0x0d8000f0|32|LT_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
+
{{rla|0x0d8000f0|32|HW_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
{{rla|0x0d8000f4|32|LT_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
+
{{rla|0x0d8000f4|32|HW_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
{{rla|0x0d8000f8|32|LT_GPIO_INMIR|GPIO Input Mirror (Starbuck only)}}
+
{{rla|0x0d8000f8|32|HW_GPIO_STRAPS|GPIO Straps (Starbuck only)}}
{{rla|0x0d8000fc|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
+
{{rla|0x0d8000fc|32|HW_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
 
|}
 
|}
      −
{{reglist|Latte GPIOs (group 2)}}
+
{{reglist|Latte GPIOs (LT)}}
{{rla|0x0d800520|32|LT_GPIO2E_OUT|GPIO Outputs (Espresso access)}}
+
{{rla|0x0d800520|32|LT_GPIOB_OUT|GPIO Outputs (Espresso access)}}
{{rla|0x0d800524|32|LT_GPIOE2_DIR|GPIO Direction (Espresso access)}}
+
{{rla|0x0d800524|32|LT_GPIOB_DIR|GPIO Direction (Espresso access)}}
{{rla|0x0d800528|32|LT_GPIOE2_IN|GPIO Inputs (Espresso access)}}
+
{{rla|0x0d800528|32|LT_GPIOB_IN|GPIO Inputs (Espresso access)}}
{{rla|0x0d80052c|32|LT_GPIOE2_INTLVL|GPIO Interrupt Levels (Espresso access)}}
+
{{rla|0x0d80052c|32|LT_GPIOB_INTLVL|GPIO Interrupt Levels (Espresso access)}}
{{rla|0x0d800530|32|LT_GPIOE2_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
+
{{rla|0x0d800530|32|LT_GPIOB_INTFLAG|GPIO Interrupt Flags (Espresso access)}}
{{rla|0x0d800534|32|LT_GPIOE2_INTMASK|GPIO Interrupt Masks (Espresso access)}}
+
{{rla|0x0d800534|32|LT_GPIOB_INTMASK|GPIO Interrupt Masks (Espresso access)}}
{{rla|0x0d800538|32|LT_GPIOE2_INMIR|GPIO Input Mirror (Espresso access)}}
+
{{rla|0x0d800538|32|LT_GPIOB_STRAPS|GPIO Straps (Espresso access)}}
{{rla|0x0d80053c|32|LT_GPIO2_ENABLE|GPIO Enable (Starbuck only)}}
+
{{rla|0x0d80053c|32|LT_GPIO_ENABLE|GPIO Enable (Starbuck only)}}
{{rla|0x0d800540|32|LT_GPIO2_OUT|GPIO Outputs (Starbuck only)}}
+
{{rla|0x0d800540|32|LT_GPIO_OUT|GPIO Outputs (Starbuck only)}}
{{rla|0x0d800544|32|LT_GPIO2_DIR|GPIO Direction (Starbuck only)}}
+
{{rla|0x0d800544|32|LT_GPIO_DIR|GPIO Direction (Starbuck only)}}
{{rla|0x0d800548|32|LT_GPIO2_IN|GPIO Inputs (Starbuck only)}}
+
{{rla|0x0d800548|32|LT_GPIO_IN|GPIO Inputs (Starbuck only)}}
{{rla|0x0d80054c|32|LT_GPIO2_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
+
{{rla|0x0d80054c|32|LT_GPIO_INTLVL|GPIO Interrupt Levels (Starbuck only)}}
{{rla|0x0d800550|32|LT_GPIO2_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
+
{{rla|0x0d800550|32|LT_GPIO_INTFLAG|GPIO Interrupt Flags (Starbuck only)}}
{{rla|0x0d800554|32|LT_GPIO2_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
+
{{rla|0x0d800554|32|LT_GPIO_INTMASK|GPIO Interrupt Masks (Starbuck only)}}
{{rla|0x0d800558|32|LT_GPIO2_INMIR|GPIO Input Mirror (Starbuck only)}}
+
{{rla|0x0d800558|32|LT_GPIO_STRAPS|GPIO Straps (Starbuck only)}}
{{rla|0x0d80055c|32|LT_GPIO2_OWNER|GPIO Owner Select (Starbuck only)}}
+
{{rla|0x0d80055c|32|LT_GPIO_OWNER|GPIO Owner Select (Starbuck only)}}
 
|}
 
|}
    
== Register descriptions ==
 
== Register descriptions ==
{{regsimple2|LT_GPIO_ENABLE|addr=0x0d8000dc|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIO_ENABLE|addr=0x0d8000dc|bits=32|split=24|access=R/W}}
 
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
 
The bits of this register indicate whether specific GPIO pins are enabled. The typical value is 0xFFFFFF, to enable all pins.
 
----
 
----
{{regsimple2|LT_GPIO_OUT|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIO_OUT|addr=0x0d8000e0|bits=32|split=24|access=R/W}}
 
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
 
This register contains the output value for all pins. These only take effect if the pin is configured as an output.
 
----
 
----
{{regsimple2|LT_GPIO_DIR|addr=0x0d8000e4|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIO_DIR|addr=0x0d8000e4|bits=32|split=24|access=R/W}}
 
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
 
A '1' bit for a pin indicates that it will behave as an output (drive), while a '0' bit tristates the pin and it becomes a high-impedance input.
 
----
 
----
{{regsimple2|LT_GPIO_IN|addr=0x0d8000e8|bits=32|split=24|access=R}}
+
{{regsimple2|HW_GPIO_IN|addr=0x0d8000e8|bits=32|split=24|access=R}}
 
This register can be read to obtain the current input value of the GPIO pins.
 
This register can be read to obtain the current input value of the GPIO pins.
 
----
 
----
{{regsimple2|LT_GPIO_INTLVL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIO_INTLVL|addr=0x0d8000ec|bits=32|split=24|access=R/W}}
 
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
 
Configures the pin state that causes an interrupt. If a bit is set in this register, the pin causes an interrupt when high. A zero causes the opposite behavior.
 
----
 
----
{{regsimple2|LT_GPIO_INTFLAG|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}
+
{{regsimple2|HW_GPIO_INTFLAG|addr=0x0d8000f0|bits=32|split=24|access=R/Z}}
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the LT_GPIO_INTLVL register, then the corresponding bit in LT_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in LT_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
+
Bits in this register indicate which pins have triggered their interrupt flags. Write one to clear a bit back to zero. The bits can only be cleared if the pin is in the idle state: if the pin state equals the value in the HW_GPIO_INTLVL register, then the corresponding bit in HW_GPIO_INTFLAG will be stuck at one until the pin state reverts or the value in HW_GPIO_INTLVL is inverted. Once the pin is idle, the bits in this register may be cleared by writing one to them.
 
----
 
----
{{regsimple2|LT_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIO_INTMASK|addr=0x0d8000f4|bits=32|split=24|access=R/W}}
Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|Latte GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in [[#LT_GPIO_INTFLAG|LT_GPIO_INTFLAG]]. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is LT_GPIO_INTMASK & LT_GPIO_INTFLAG & ~LT_GPIO_OWNER.
+
Only the bits set in this register propagate their interrupts to the master [[Hardware/Latte_IRQ_Controller|Latte GPIO interrupt]] (#11). All other pin interrupts are ignored, although the interrupt state can still be queried and cleared in HW_GPIO_INTFLAG. Note: Pins configured for Espresso access do not generate Latte IRQ #11. Instead, they generate Latte IRQ #10. In other words, the IRQ generation logic for #11 is HW_GPIO_INTMASK & HW_GPIO_INTFLAG & ~LT_GPIO_OWNER.
 
----
 
----
{{regsimple2|LT_GPIO_INMIR|addr=0x0d8000f8|bits=32|split=24|access=R}}
+
{{regsimple2|HW_GPIO_STRAPS|addr=0x0d8000f8|bits=32|split=24|access=R}}
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible. {{check}}
+
This register appears to contain the input state at some point in time, possibly power-on or interrupt or something like that. Writes do not seem possible.
 
----
 
----
{{regsimple2|LT_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIO_OWNER|addr=0x0d8000fc|bits=32|split=24|access=R/W}}
This register configures which pins can be controlled by the LT_GPIOE registers. A one bit configures the pin for control via the LT_GPIOE registers, which lets it be accessed by the Espresso. A zero bit restricts access to the LT_GPIO registers, which are Starbuck-only. The LT_GPIO registers always have read access to all pins, but any writes (changes) must go through the LT_GPIOE registers if the corresponding bit is set in the LT_GPIO_OWNER register.
+
This register configures which pins can be controlled by the HW_GPIOB_* registers. A one bit configures the pin for control via the LT_GPIOE registers, which lets it be accessed by the Espresso. A zero bit restricts access to the HW_GPIO_* registers, which are Starbuck-only. The HW_GPIO_* registers always have read access to all pins, but any writes (changes) must go through the HW_GPIOB_* registers if the corresponding bit is set in the HW_GPIO_OWNER register.
 
----
 
----
{{regsimple2|LT_GPIOE_OUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIOB_OUT|addr=0x0d8000c0|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE_DIR|addr=0x0d8000c4|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIOB_DIR|addr=0x0d8000c4|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE_IN|addr=0x0d8000c8|bits=32|split=24|access=R}}
+
{{regsimple2|HW_GPIOB_IN|addr=0x0d8000c8|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOE_INTLVL|addr=0x0d8000cc|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIOB_INTLVL|addr=0x0d8000cc|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}
+
{{regsimple2|HW_GPIOB_INTFLAG|addr=0x0d8000d0|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIOE_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
+
{{regsimple2|HW_GPIOB_INTMASK|addr=0x0d8000d4|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE_INMIR|addr=0x0d8000d8|bits=32|split=24|access=R}}
+
{{regsimple2|HW_GPIOB_STRAPS|addr=0x0d8000d8|bits=32|split=24|access=R}}
These registers operate identically to their LT_GPIO counterparts above, but they only control the pins which have their respective [[#LT_GPIO_OWNER|LT_GPIO_OWNER]] bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the [[Hardware/Latte_IRQ_Controller|Latte GPIOE interrupt]] (#10). The generation logic would be LT_GPIOE_INTFLAG & LT_GPIOE_INTMASK, with an implicit AND with LT_GPIO_OWNER since the GPIOE registers are already masked with the LT_GPIO_OWNER register.
+
These registers operate identically to their HW_GPIO_* counterparts above, but they only control the pins which have their respective HW_GPIO_OWNER bits set to 1. They can be accessed by the Espresso as well as the Starbuck. The master interrupt feeds to the [[Hardware/Latte_IRQ_Controller|Latte GPIOE interrupt]] (#10). The generation logic would be HW_GPIOB_INTFLAG & HW_GPIOB_INTMASK, with an implicit AND with HW_GPIO_OWNER since the HW_GPIOB_* registers are already masked with the HW_GPIO_OWNER register.
   −
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the LT_GPIO registers, and that bit is then set in the LT_GPIO_OWNER register, those settings will immediately be visible in the LT_GPIOE registers. There is only one set of data registers, and the LT_GPIO_OWNER register just controls the access that the LT_GPIOE registers have to that data.
+
When switching owners, copying of the data is not necessary. For example, if pin 0 has certain configuration in the HW_GPIO_* registers, and that bit is then set in the HW_GPIO_OWNER register, those settings will immediately be visible in the HW_GPIOB_* registers. There is only one set of data registers, and the HW_GPIO_OWNER register just controls the access that the HW_GPIOB_* registers have to that data.
 
----
 
----
{{regsimple2|LT_GPIO2_ENABLE|addr=0x0d80053c|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIOB_OUT|addr=0x0d800520|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_OUT|addr=0x0d800540|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIOB_DIR|addr=0x0d800524|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_DIR|addr=0x0d800544|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIOB_IN|addr=0x0d800528|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO2_IN|addr=0x0d800548|bits=32|split=24|access=R}}
+
{{regsimple2|LT_GPIOB_INTLVL|addr=0x0d80052c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_INTLVL|addr=0x0d80054c|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIOB_INTFLAG|addr=0x0d800530|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIO2_INTFLAG|addr=0x0d800550|bits=32|split=24|access=R/Z}}
+
{{regsimple2|LT_GPIOB_INTMASK|addr=0x0d800534|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_INTMASK|addr=0x0d800554|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIOB_STRAPS|addr=0x0d800538|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIO2_INMIR|addr=0x0d800558|bits=32|split=24|access=R}}
+
{{regsimple2|LT_GPIO_ENABLE|addr=0x0d80053c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIO2_OWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIO_OUT|addr=0x0d800540|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_OUT|addr=0x0d800520|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIO_DIR|addr=0x0d800544|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_DIR|addr=0x0d800524|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIO_IN|addr=0x0d800548|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOE2_IN|addr=0x0d800528|bits=32|split=24|access=R}}
+
{{regsimple2|LT_GPIO_INTLVL|addr=0x0d80054c|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_INTLVL|addr=0x0d80052c|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIO_INTFLAG|addr=0x0d800550|bits=32|split=24|access=R/Z}}
{{regsimple2|LT_GPIOE2_INTFLAG|addr=0x0d800530|bits=32|split=24|access=R/Z}}
+
{{regsimple2|LT_GPIO_INTMASK|addr=0x0d800554|bits=32|split=24|access=R/W}}
{{regsimple2|LT_GPIOE2_INTMASK|addr=0x0d800534|bits=32|split=24|access=R/W}}
+
{{regsimple2|LT_GPIO_STRAPS|addr=0x0d800558|bits=32|split=24|access=R}}
{{regsimple2|LT_GPIOE2_INMIR|addr=0x0d800538|bits=32|split=24|access=R}}
+
{{regsimple2|LT_GPIO_OWNER|addr=0x0d80055c|bits=32|split=24|access=R/W}}
These registers are identical to those used for the first GPIO group.
+
These registers work identically to those used for the first GPIO group.
76

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