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−
−
== Register List ==
== Register List ==
−{{reglist|Latte GPIOs}}
+{{reglist|OTP}}
−{{rla|0x0d8001ec|32|LT_OTP_COMMAND|OTP command}}
+{{rla|0x0d8001ec|32|HW_OTPCMD|OTP command}}
−{{rla|0x0d8001f0|32|LT_OTP_DATA|OTP data}}
+{{rla|0x0d8001f0|32|HW_OTPDATA|OTP data}}
|}
|}
== General Registers ==
== General Registers ==
−{{reg32 | LT_OTP_COMMAND | addr = 0x0d8001ec | hifields = 2 | lofields = 2 |
+{{reg32 | HW_OTPCMD | addr = 0x0d8001ec | hifields = 2 | lofields = 2 |
|1|15|
|1|15|
|R/W|U|
|R/W|U|
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}}
}}
{{regdesc
{{regdesc
−|RD|Set to one to execute a read command. If clear, then the data in LT_OTP_DATA is unchanged.
+|RD|Set to one to execute a read command. If clear, then the data in HW_OTPDATA is unchanged.
|ADDR|Word address to read. 0x00 to 0x1F (32 4byte words) ORed with the bank's number (0x000 to 0x700).
|ADDR|Word address to read. 0x00 to 0x1F (32 4byte words) ORed with the bank's number (0x000 to 0x700).
}}
}}
This register contains the command sent to the OTP. It is unknown whether is register is also used during the factory process to program the OTP.
This register contains the command sent to the OTP. It is unknown whether is register is also used during the factory process to program the OTP.
----
----
−{{regsimple|LT_OTP_DATA|addr=0x0d8001f0|bits=32|access=R}}
+{{regsimple|HW_OTPDATA|addr=0x0d8001f0|bits=32|access=R}}
−This register contains the output data for the last issued OTP read command. The execution of a read operation via the LT_OTP_COMMAND register immediately changes this register without any delay.
+This register contains the output data for the last issued OTP read command. The execution of a read operation via the HW_OTPCMD register immediately changes this register without any delay.
== IOSU ==
== IOSU ==
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word_addr = word_addr | word_offset;
word_addr = word_addr | word_offset;
*(u32*)0x0D8001EC = word_addr; // Write to LT_OTPCMD
+ *(u32*)0x0D8001EC = word_addr; // Write to HW_OTPCMD
− u32 temp = *(u32*)0x0D8001EC; // Read from LT_OTPCMD (sync?)
+ u32 temp = *(u32*)0x0D8001EC; // Read from HW_OTPCMD (sync?)
*(u32*)(out_buf + step) = *(u32*)0x0D8001F0; // Copy from LT_OTPDATA
+ *(u32*)(out_buf + step) = *(u32*)0x0D8001F0; // Copy from HW_OTPDATA
step += 4;
step += 4;
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|-
|-
| 1 (Wii U bank) || 0x084 (0x21 * 4) || 0x04 bytes || IOStrength configuration flags
| 1 (Wii U bank) || 0x084 (0x21 * 4) || 0x04 bytes || IOStrength configuration flags
− Flag 0x00008000 sets register LT_IOSTRENGTH_CTRL0.
+ Flag 0x00008000 sets register HW_IOSTRCTRL0.
− Flags 0x00000008, 0x00000080, 0x00000800, 0x00002000 set register LT_IOSTRENGTH_CTRL1.
+ Flags 0x00000008, 0x00000080, 0x00000800, 0x00002000 set register HW_IOSTRCTRL1.
Should be 0x00000000 in retail units.
Should be 0x00000000 in retail units.
|-
|-
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| 5 (Wii U certificate bank) || 0x2C8 (0xB2 * 4) || 0x18 bytes || Unknown (unused)
| 5 (Wii U certificate bank) || 0x2C8 (0xB2 * 4) || 0x18 bytes || Unknown (unused)
|-
|-
−| 5 (Wii U certificate bank) || 0x2E0 (0xB8 * 4) || 0x20 bytes || Unknown (locked out by boot1)
+| 5 (Wii U certificate bank) || 0x2E0 (0xB8 * 4) || 0x20 bytes || Unknown (locked out by boot1, unused)
|-
|-
| 6 (Wii certificate bank) || 0x300 (0xC0 * 4) || 0x04 bytes || Wii root certificate MS ID
| 6 (Wii certificate bank) || 0x300 (0xC0 * 4) || 0x04 bytes || Wii root certificate MS ID
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Only 0x1E bytes are used.
Only 0x1E bytes are used.
|-
|-
−| 7 (Misc bank) || 0x380 (0xE0 * 4) || 0x20 bytes || Unknown (locked out by boot1)
+| 7 (Misc bank) || 0x380 (0xE0 * 4) || 0x20 bytes || Unknown (locked out by boot1, unused)
|-
|-
| 7 (Misc bank) || 0x3A0 (0xE8 * 4) || 0x10 bytes || Wii U boot1 key (locked out by boot0)
| 7 (Misc bank) || 0x3A0 (0xE8 * 4) || 0x10 bytes || Wii U boot1 key (locked out by boot0)