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Hardware/Latte registers (view source)
Revision as of 12:24, 28 December 2019
, 12:24, 28 December 2019Document HW_IOSTRCTRL0 according to IOS-BSP
Line 106:
Line 106:
{{rld|0x0d8001d8|32|HW_PLLUSBEXT}}
{{rld|0x0d8001d8|32|HW_PLLUSBEXT}}
{{rld|0x0d8001dc|32|HW_IOPWRCTRL|I/O power control}}
{{rld|0x0d8001dc|32|HW_IOPWRCTRL|I/O power control}}
−{{rld|0x0d8001e0|32|HW_IOSTRCTRL0|I/O power strength control}}
+{{rla|0x0d8001e0|32|HW_IOSTRCTRL0|I/O power strength control}}
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
{{rld|0x0d8001e4|32|HW_IOSTRCTRL1|I/O power strength control}}
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL|Clock power strength control}}
{{rld|0x0d8001e8|32|HW_CLKSTRCTRL|Clock power strength control}}
Line 270:
Line 270:
|VERHI|Version
|VERHI|Version
|VERLO|Revision
|VERLO|Revision
+}}
+
+{{reg32 | HW_IOSTRCTRL0 | addr = 0x0d8001e0 | hifields = 6 | lofields = 6 |
+|2 |3 |3 |3 |3 |2 |
+|? |? |? |R/W |R/W |? |
+| | | |VI |DI | ||
+|1 |3 |3 |3 |3 |3 |
+|? |? |? |R/W |? |R/W |
+| | | |SI | |AI |
+}}
+{{regdesc
+|VI|Video Interface IO power control. IOSU sets to 0x3 on Hollywood hardware, or 0x1 on Bollywood or Latte hardware.
+|DI|[[Hardware/Legacy#Drive_Interface|Drive Interface]] IO power control. IOSU sets to 0x1 on Hollywood hardware, or 0x2 on Bollywood or Latte hardware.
+|SI|[[Hardware/Legacy#Serial_Interface|Serial Interface]] IO power control. IOSU sets to 0x1 on Hollywood and Bollywood chipsets, 0x2 on Latte chips.
+|AI|[[Hardware/Legacy#Audio_Interface|Audio Interface]] IO power control. IOSU sets to 0x2 on Hollywood hardware, or 0x1 on Bollywood or Latte hardware.
}}
}}