Changes

Jump to navigation Jump to search
Add AV I²C registers, rename existing registers to "SMC_I2C"
Line 37: Line 37:  
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
 
{{rld|0x0d800060|32|HW_SRNPROT|SRAM access control}}
 
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
 
{{rld|0x0d800064|32|HW_BUSPROT|AHB access control}}
{{rld|0x0d800068|32|UNKNOWN|Unknown}}
+
<!-- check: are these really Latte-only? -->
{{rld|0x0d80006c|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800068|32|LT_AVE_I2C_INT_MASK{{check}}|[[Hardware/Latte I²C|Latte I²C]] (AV encoder)|drs=2}}
 +
{{rld|0x0d80006c|32|LT_AVE_I2C_INT_STATE}}
 
{{rld|0x0d800070|32|HW_AIP_PROT|[[Hardware/EXI|EXI]] access control}}
 
{{rld|0x0d800070|32|HW_AIP_PROT|[[Hardware/EXI|EXI]] access control}}
 
{{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}}
 
{{rld|0x0d800074|32|HW_AIP_IOCTRL|Unknown}}
Line 121: Line 122:  
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rla|0x0d800214|32|HW_CHIPREVID|Hardware version (Wood)}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800224|32|UNKNOWN|Unknown}}
{{rld|0x0d800250|32|UNKNOWN|Unknown}}
+
<!-- check: are these really Latte-only? -->
{{rld|0x0d800254|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800250|32|LT_AVE_I2C_CLOCK{{check}}|[[Hardware/Latte I²C|Latte I²C]] (AV encoder)|drs=4}}
{{rld|0x0d800258|32|UNKNOWN|Unknown}}
+
{{rld|0x0d800254|32|LT_AVE_I2C_INOUT_DATA}}
 +
{{rld|0x0d800258|32|LT_AVE_I2C_INOUT_CTRL}}
 +
{{rld|0x0d80025c|32|LT_AVE_I2C_INOUT_SIZE}}
 
{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800400|32|LT_IPC_PPCMSG0|[[Hardware/IPC|Latte IPC]] (per-core)|drs=12}}
 
{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
 
{{rld|0x0d800404|32|LT_IPC_PPCCTRL0}}
Line 184: Line 187:  
{{rld|0x0d800558|32|LT_GPIO_STRAPS}}
 
{{rld|0x0d800558|32|LT_GPIO_STRAPS}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER}}
 
{{rld|0x0d80055c|32|LT_GPIO_OWNER}}
{{rld|0x0d800570|32|LT_I2C_CLOCK|I2C related|drs=6}}
+
{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK|[[Hardware/Latte I²C|Latte I²C]] (SMC)|drs=6}}
{{rld|0x0d800574|32|LT_I2C_INOUT_DATA}}
+
{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
{{rld|0x0d800578|32|LT_I2C_INOUT_CTRL}}
+
{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
{{rld|0x0d80057c|32|LT_I2C_INOUT_SIZE}}
+
{{rld|0x0d80057c|32|LT_SMC_I2C_INOUT_SIZE}}
{{rld|0x0d800580|32|LT_I2C_INT_MASK}}
+
{{rld|0x0d800580|32|LT_SMC_I2C_INT_MASK}}
{{rld|0x0d800584|32|LT_I2C_INT_STATE}}
+
{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
 
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
 
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|Debug mode flags}}
 
{{rla|0x0d8005a4|32|LT_DEBUG|Debug mode flags}}

Navigation menu