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work-in-progress I²C page. Need to check what the "channel" parameter is before continuing - my undertstanding of "buses" might be incorrect.
{{Infobox MMIO
| partof = {{hw|Latte Registers}}
| arm = Full
| ppc = Partial
| base = 0x0d800000, 0x0d800570
| len = 0x6
| bits = 32
| ppcirq = 4
| latteirq = 13, 14
}}
{{Incomplete}}
(this article is a work-in-progress based on reverse-engineered code, the concepts presented here [buses, GPIO] have not been tested!)
The Latte includes dedicated hardware to communicate with the console's I²C devices, along with the [http://www.gc-linux.org/wiki/AVE-RVL GPIO-twiddling method] used on the Wii.
== Buses ==
Each pair of I²C lines available as {{hw|Latte GPIOs}} appears to have an equivalent Latte controller. Since I²C
=== Bus 1 (AV encoder) ===
This bus, using GPIO lines AV0I2CClock and AV0I2CData, are used to communicate with the Wii U's AV encoder, responsible for HDMI output. It's primarily accessed by [[tve.rpl]] from Cafe OS userspace. See {{hw|AV Encoder}}.
=== Bus 2 (AV encoder #2) ===
{{IncompleteSection}}
The existence of this bus is implied by the AV1I2CClock and AV1I2CData GPIO lines, though what it's used for or where its Latte controller might be are currently unknown.
=== Bus 3 (SMC) ===
This bus is used by [[IOSU]] to communicate with the onboard {{hw|SMC}} management chip, which handles miscellaneous functions like the power LED and ejecting the disc drive.
== Registers ==
{{reglist|I²C Bus 1 Registers (AV encoder)}}
{{rld|0x0d800068|32|LT_AVE_I2C_INT_MASK|}}
{{rld|0x0d80006c|32|LT_AVE_I2C_INT_STATE}}
{{rld|0x0d800250|32|LT_AVE_I2C_CLOCK|}}
{{rld|0x0d800254|32|LT_AVE_I2C_INOUT_DATA}}
{{rld|0x0d800258|32|LT_AVE_I2C_INOUT_CTRL}}
{{rld|0x0d80025c|32|LT_AVE_I2C_INOUT_SIZE}}
|}
Despite being in the Wood address space, these registers do not appear to be present on the original Wii.{{check}}
{{reglist|I²C Bus 3 Registers (SMC)}}
{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK}}
{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
{{rld|0x0d80057c|32|LT_SMC_I2C_INOUT_SIZE}}
{{rld|0x0d800580|32|LT_SMC_I2C_INT_MASK}}
{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
|}
| partof = {{hw|Latte Registers}}
| arm = Full
| ppc = Partial
| base = 0x0d800000, 0x0d800570
| len = 0x6
| bits = 32
| ppcirq = 4
| latteirq = 13, 14
}}
{{Incomplete}}
(this article is a work-in-progress based on reverse-engineered code, the concepts presented here [buses, GPIO] have not been tested!)
The Latte includes dedicated hardware to communicate with the console's I²C devices, along with the [http://www.gc-linux.org/wiki/AVE-RVL GPIO-twiddling method] used on the Wii.
== Buses ==
Each pair of I²C lines available as {{hw|Latte GPIOs}} appears to have an equivalent Latte controller. Since I²C
=== Bus 1 (AV encoder) ===
This bus, using GPIO lines AV0I2CClock and AV0I2CData, are used to communicate with the Wii U's AV encoder, responsible for HDMI output. It's primarily accessed by [[tve.rpl]] from Cafe OS userspace. See {{hw|AV Encoder}}.
=== Bus 2 (AV encoder #2) ===
{{IncompleteSection}}
The existence of this bus is implied by the AV1I2CClock and AV1I2CData GPIO lines, though what it's used for or where its Latte controller might be are currently unknown.
=== Bus 3 (SMC) ===
This bus is used by [[IOSU]] to communicate with the onboard {{hw|SMC}} management chip, which handles miscellaneous functions like the power LED and ejecting the disc drive.
== Registers ==
{{reglist|I²C Bus 1 Registers (AV encoder)}}
{{rld|0x0d800068|32|LT_AVE_I2C_INT_MASK|}}
{{rld|0x0d80006c|32|LT_AVE_I2C_INT_STATE}}
{{rld|0x0d800250|32|LT_AVE_I2C_CLOCK|}}
{{rld|0x0d800254|32|LT_AVE_I2C_INOUT_DATA}}
{{rld|0x0d800258|32|LT_AVE_I2C_INOUT_CTRL}}
{{rld|0x0d80025c|32|LT_AVE_I2C_INOUT_SIZE}}
|}
Despite being in the Wood address space, these registers do not appear to be present on the original Wii.{{check}}
{{reglist|I²C Bus 3 Registers (SMC)}}
{{rld|0x0d800570|32|LT_SMC_I2C_CLOCK}}
{{rld|0x0d800574|32|LT_SMC_I2C_INOUT_DATA}}
{{rld|0x0d800578|32|LT_SMC_I2C_INOUT_CTRL}}
{{rld|0x0d80057c|32|LT_SMC_I2C_INOUT_SIZE}}
{{rld|0x0d800580|32|LT_SMC_I2C_INT_MASK}}
{{rld|0x0d800584|32|LT_SMC_I2C_INT_STATE}}
|}