In memory of Ben “bushing” Byer, who passed away on Monday, February 8th, 2016.

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Hardware/Latte registers (view source)

Revision as of 01:21, 7 April 2023

501 bytes added ,  01:21, 7 April 2023
c2w.elf my beloved,
Line 206: Line 206:  
{{rld|0x0d8005e8|32|LT_IFPWRCTRL|Interface power control}}
 
{{rld|0x0d8005e8|32|LT_IFPWRCTRL|Interface power control}}
 
{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
 
{{rld|0x0d8005ec|32|LT_PLLSYS|System PLL configuration}}
−
{{rld|0x0d800620|32|LT_ABIF_CPLTL_ADDR|ASIC bus interface|drs=2}}
+
{{rld|0x0d800620|32|LT_ABIF_ADDR|ASIC bus interface|drs=2}}
−
{{rld|0x0d800624|32|LT_ABIF_CPLTL_DATA}}
+
{{rld|0x0d800624|32|LT_ABIF_DATA}}
 
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800628|32|UNKNOWN|Unknown}}
 
{{rld|0x0d800640|32|LT_60XE_CFG|60Xe data bus configuration}}
 
{{rld|0x0d800640|32|LT_60XE_CFG|60Xe data bus configuration}}
Line 337: Line 337:  
{{regdesc
 
{{regdesc
 
|BOOT1|Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7
 
|BOOT1|Clearing bit 29 (mask value of 0xDFFFFFFF) locks out boot1's AES-128 key from OTP bank 7
 +
}}
 +
 +
{{reg32 | LT_ABIF_ADDR | addr = 0x0d800620 | hifields = 3 | lofields = 1 |
 +
|2        |6    |8    |
 +
|R/W      |R/W  |?    |
 +
|tile_id  | device| ||
 +
|16        |
 +
|R/W      |
 +
|offset    |
 +
}}
 +
The ASIC bus interface register indexes a set of registers
 +
{{regdesc
 +
|tile_id|Might only be applicable for device 0, CplCt
 +
|device |See below
 +
|offset |Offset into registers, acccessed through LT_ABIF_DATA. Might be 24-bit?
 +
}}
 +
'''device''' values:
 +
{{regdesc
 +
|0x0|CplCt
 +
|0x1|CplTr
 +
|0x2|CplTl
 +
|0x3|CplBr
 +
|0x4|CplBl
 +
|0xC|GPU
 
}}
 
}}
    
{{hwstub}}
 
{{hwstub}}
Retrieved from "https://wiiubrew.org/wiki/Special:MobileDiff/3577"

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