Changes

== Register List ==

== Register List ==

{{reglist|OTP}}

{{reglist|OTP}}

{{rla|0x0d8001ec|32|HW_OTPCMD|OTP command}}

{{rla|0x0d8001ec|32|HW_EFUSEADDR|OTP command}}

{{rla|0x0d8001f0|32|HW_OTPDATA|OTP data}}

{{rla|0x0d8001f0|32|HW_EFUSEDATA|OTP data}}

|}

|}

== General Registers ==

== General Registers ==

{{reg32 | HW_OTPCMD | addr = 0x0d8001ec | hifields = 2 | lofields = 4 |

{{reg32 | HW_EFUSEADDR | addr = 0x0d8001ec | hifields = 2 | lofields = 4 |

|1|15|

|1|15|

|R/W|U|

|R/W|U|

}}

}}

{{regdesc

{{regdesc

|RD|Set to one to execute a read command. If clear, then the data in HW_OTPDATA is unchanged.

|RD|Set to one to execute a read command. If clear, then the data in HW_EFUSEDATA is unchanged.

|BANK|Bank's number (0x0 to 0x7).

|BANK|Bank's number (0x0 to 0x7).

|ADDR|Word address to read, 0x00 to 0x1F (32 4byte words).

|ADDR|Word address to read, 0x00 to 0x1F (32 4byte words).

This register contains the command sent to the OTP. It is unknown whether is register is also used during the factory process to program the OTP.

This register contains the command sent to the OTP. It is unknown whether is register is also used during the factory process to program the OTP.

----

----

{{regsimple|HW_OTPDATA|addr=0x0d8001f0|bits=32|access=R}}

{{regsimple|HW_EFUSEDATA|addr=0x0d8001f0|bits=32|access=R}}

This register contains the output data for the last issued OTP read command. The execution of a read operation via the HW_OTPCMD register immediately changes this register without any delay.

This register contains the output data for the last issued OTP read command. The execution of a read operation via the HW_EFUSEADDR register immediately changes this register without any delay.

== IOSU ==

== IOSU ==

       word_addr = word_addr | word_offset;

       word_addr = word_addr | word_offset;

        

        

       *(u32*)0x0D8001EC = word_addr;                    // Write to HW_OTPCMD

       *(u32*)0x0D8001EC = word_addr;                    // Write to HW_EFUSEADDR

         u32 temp = *(u32*)0x0D8001EC;                    // Read from HW_OTPCMD (sync?)

         u32 temp = *(u32*)0x0D8001EC;                    // Read from HW_EFUSEADDR

        

        

       *(u32*)(out_buf + step) = *(u32*)0x0D8001F0;      // Copy from HW_OTPDATA

       *(u32*)(out_buf + step) = *(u32*)0x0D8001F0;      // Copy from HW_EFUSEDATA

        

        

       step += 4;

       step += 4;