102
edits
Changes
MEMCMPT ppcClkMult bit
Line 208:
Line 208:
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
{{rla|0x0d8005a0|32|LT_CHIPREVID|Hardware version (Latte)}}
{{rla|0x0d8005a4|32|LT_SYSCFG1|Debug mode flags}}
{{rla|0x0d8005a4|32|LT_SYSCFG1|Debug mode flags}}
−{{rld|0x0d8005b0|32|LT_MEMCMPT|Memory compat mode for Wood}}
+{{rla|0x0d8005b0|32|LT_MEMCMPT|Memory compat mode for Wood}}
{{rld|0x0d8005b4|32|LT_AHBCMPT|AHB compat mode for Wood}}
{{rld|0x0d8005b4|32|LT_AHBCMPT|AHB compat mode for Wood}}
{{rld|0x0d8005b8|32|LT_AICMPT|AI compat mode for Wood}}
{{rld|0x0d8005b8|32|LT_AICMPT|AI compat mode for Wood}}
Line 508:
Line 508:
|DBG_HALT|Halts the IOSU's boot sequence and waits for user input from JTAG.
|DBG_HALT|Halts the IOSU's boot sequence and waits for user input from JTAG.
|SLC_EMU|Emulate SLC on host.
|SLC_EMU|Emulate SLC on host.
+}}
+
+{{reg32 | LT_MEMCMPT | addr = 0x0d8005b0 | hifields = 1 | lofields = 3 |
+|16 |
+|? |
+| ||
+|10 |1 |5 |
+|? |R/W|? |
+| |PPC_COMPAT| |
+}}
+{{regdesc
+|PPC_COMPAT|If set, PPC clocks are 3x SYSPLL. If unset, PPC clocks are 5x SYSPLL. In [[IOSU]], this bit is set based on [[Hardware/SEEPROM|SEEPROM]]'s ppcClockMultiplier value.
}}
}}