Changes

{{rld|0x0d80042c|32|LT_IPCIOPCTRL2}}

{{rld|0x0d80042c|32|LT_IPCIOPCTRL2}}

{{rld|0x0d800440|32|LT_PPC0INTSTSALL|[[Hardware/Latte_IRQ_Controller|Latte IRQs]] (per-core)|drs=18}}

{{rld|0x0d800440|32|LT_PPC0INTSTSALL|[[Hardware/Latte_IRQ_Controller|Latte IRQs]] (per-core)|drs=18}}

{{rld|0x0d800444|32|LT_PPC0INTSTSLT}}

{{rld|0x0d800444|32|LT_PPC0INTSTSLATTE}}

{{rld|0x0d800448|32|LT_PPC0INTENALL}}

{{rld|0x0d800448|32|LT_PPC0INTENALL}}

{{rld|0x0d80044c|32|LT_PPC0INTENLT}}

{{rld|0x0d80044c|32|LT_PPC0INTENLATTE}}

{{rld|0x0d800450|32|LT_PPC1INTSTSALL}}

{{rld|0x0d800450|32|LT_PPC1INTSTSALL}}

{{rld|0x0d800454|32|LT_PPC1INTSTSLT}}

{{rld|0x0d800454|32|LT_PPC1INTSTSLATTE}}

{{rld|0x0d800458|32|LT_PPC1INTENALL}}

{{rld|0x0d800458|32|LT_PPC1INTENALL}}

{{rld|0x0d80045c|32|LT_PPC1INTENLT}}

{{rld|0x0d80045c|32|LT_PPC1INTENLATTE}}

{{rld|0x0d800460|32|LT_PPC2INTSTSALL}}

{{rld|0x0d800460|32|LT_PPC2INTSTSALL}}

{{rld|0x0d800464|32|LT_PPC2INTSTSLT}}

{{rld|0x0d800464|32|LT_PPC2INTSTSLATTE}}

{{rld|0x0d800468|32|LT_PPC2INTENALL}}

{{rld|0x0d800468|32|LT_PPC2INTENALL}}

{{rld|0x0d80046c|32|LT_PPC2INTENLT}}

{{rld|0x0d80046c|32|LT_PPC2INTENLATTE}}

{{rld|0x0d800470|32|LT_IOPINTSTSALL}}

{{rld|0x0d800470|32|LT_IOPINTSTSALL}}

{{rld|0x0d800474|32|LT_IOPINTSTSLT}}

{{rld|0x0d800474|32|LT_IOPINTSTSLATTE}}

{{rld|0x0d800478|32|LT_IOPIRQINTENALL}}

{{rld|0x0d800478|32|LT_IOPIRQINTENALL}}

{{rld|0x0d80047c|32|LT_IOPIRQINTENLT}}

{{rld|0x0d80047c|32|LT_IOPIRQINTENLATTE}}

{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}

{{rld|0x0d800480|32|LT_IOPFIQINTENALL}}

{{rld|0x0d800484|32|LT_IOPFIQINTENLT}}

{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE}}

{{rld|0x0d8004a0|32|LT_WDG2INTSTS|AHB Watchdog interrupt status}}

{{rld|0x0d8004a0|32|LT_WDG2INTSTS|AHB Watchdog interrupt status}}

{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|AHB DMA transfer interrupt status}}

{{rld|0x0d8004a4|32|LT_DMAADR2INTSTS|AHB DMA transfer interrupt status}}