301
edits
Changes
Hardware/Processor interface (view source)
Revision as of 03:17, 19 February 2024
, 03:17, 19 February 2024no edit summary
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== Register List ==
== Register List ==
{{reglist|Processor Interface}}
{{reglist|Processor Interface}}
−{{rla|0x0c000000|32|PI_PPCINTSTS|Triggered IRQs for the PPC core}}
+{{rla|0x0c000000|32|PI_INTSTS|Triggered IRQs}}
−{{rla|0x0c000004|32|PI_PPCINTEN|Allowed IRQs for the PPC core}}
+{{rla|0x0c000004|32|PI_INTEN|Allowed IRQs}}
−{{rla|0x0c000040|32|PI_PPC0WPUNK0|Write Gather Pipe related}}
+{{rla|0x0c000040|32|PI_WG0UNK0|Write Gather Pipe related}}
−{{rla|0x0c000044|32|PI_PPC0WPUNK1|Write Gather Pipe related}}
+{{rla|0x0c000044|32|PI_WG0UNK1|Write Gather Pipe related}}
−{{rla|0x0c000048|32|PI_PPC0WPUNK2|Write Gather Pipe related}}
+{{rla|0x0c000048|32|PI_WG0UNK2|Write Gather Pipe related}}
−{{rla|0x0c00004c|32|PI_PPC0WPUNK3|Write Gather Pipe related}}
+{{rla|0x0c00004c|32|PI_WG0UNK3|Write Gather Pipe related}}
−{{rla|0x0c000050|32|PI_PPC1WPUNK0|Write Gather Pipe related}}
+{{rla|0x0c000050|32|PI_WG1UNK0|Write Gather Pipe related}}
−{{rla|0x0c000054|32|PI_PPC1WPUNK1|Write Gather Pipe related}}
+{{rla|0x0c000054|32|PI_WG1UNK1|Write Gather Pipe related}}
−{{rla|0x0c000058|32|PI_PPC1WPUNK2|Write Gather Pipe related}}
+{{rla|0x0c000058|32|PI_WG1UNK2|Write Gather Pipe related}}
−{{rla|0x0c00005c|32|PI_PPC1WPUNK3|Write Gather Pipe related}}
+{{rla|0x0c00005c|32|PI_WG1UNK3|Write Gather Pipe related}}
−{{rla|0x0c000060|32|PI_PPC2WPUNK0|Write Gather Pipe related}}
+{{rla|0x0c000060|32|PI_WG2UNK0|Write Gather Pipe related}}
−{{rla|0x0c000064|32|PI_PPC2WPUNK1|Write Gather Pipe related}}
+{{rla|0x0c000064|32|PI_WG2UNK1|Write Gather Pipe related}}
−{{rla|0x0c000068|32|PI_PPC2WPUNK2|Write Gather Pipe related}}
+{{rla|0x0c000068|32|PI_WG2UNK2|Write Gather Pipe related}}
−{{rla|0x0c00006c|32|PI_PPC2WPUNK3|Write Gather Pipe related}}
+{{rla|0x0c00006c|32|PI_WG2UNK3|Write Gather Pipe related}}
−{{rla|0x0c000078|32|PI_PPC0INTSTS|Triggered IRQs for PPC core 0}}
+{{rla|0x0c000078|32|PI_CPU0INTSTS|Triggered IRQs for CPU 0}}
−{{rla|0x0c00007c|32|PI_PPC0INTEN|Allowed IRQs for PPC core 0}}
+{{rla|0x0c00007c|32|PI_CPU0INTEN|Allowed IRQs for CPU 0}}
−{{rla|0x0c000080|32|PI_PPC1INTSTS|Triggered IRQs for PPC core 1}}
+{{rla|0x0c000080|32|PI_CPU1INTSTS|Triggered IRQs for CPU 1}}
−{{rla|0x0c000084|32|PI_PPC1INTEN|Allowed IRQs for PPC core 1}}
+{{rla|0x0c000084|32|PI_CPU1INTEN|Allowed IRQs for CPU 1}}
−{{rla|0x0c000088|32|PI_PPC2INTSTS|Triggered IRQs for PPC core 2}}
+{{rla|0x0c000088|32|PI_CPU2INTSTS|Triggered IRQs for CPU 2}}
−{{rla|0x0c00008c|32|PI_PPC2INTEN|Allowed IRQs for PPC core 2}}
+{{rla|0x0c00008c|32|PI_CPU2INTEN|Allowed IRQs for CPU 2}}
|}
|}
== Register Details ==
== Register Details ==