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Hardware/AHM controller (view source)
Revision as of 17:28, 31 December 2024
, 17:28, 31 December 2024no edit summary
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+The AHM (AHB_MEM) was a custom bridge responsible for connecting the AHB bus to the [[Hardware/Memory Controller|Memory Controller]] in the old Hollywood's chipset.<br>+The Latte hardware contains an enhanced version of this bridge dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).<br>
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−Registers with the '''AHM_*''' prefix pertain to the old, base hardware block. Registers with the '''AHMN_*''' prefix pertain to the new, enhanced hardware block.
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= AHM =
{{Infobox MMIO
{{Infobox MMIO
+| title = AHM controller
| arm = Full
| arm = Full
| base = 0x0d8b0000
| base = 0x0d8b0000
−| len = 0x4000
+| len = 0x800
| bits = 32
| bits = 32
| ppcirq = ???
| ppcirq = ???
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}}
}}
−AHM (short for AHB_MEM) is a custom bridge responsible for connecting the AHB bus to the [[Hardware/Memory Controller|Memory Controller]].
−== Register List ==
== Register List ==
−{{reglist|AHMN Controller}}
+{{reglist|AHM controller}}
−{{rld|0x0d8b0000|32|AHM_PROTDDR|AHM configuration for DDR protection}}
+{{rld|0x0d8b0000|32|AHM_SECDDR|AHM DDR memory security}}
−{{rld|0x0d8b0004|32|AHM_PROTSPL|AHM configuration for SPL protection}}
+{{rld|0x0d8b0004|32|AHM_SECSPL|AHM SPLASH memory security}}
−{{rld|0x0d8b0008|32|AHM_RDBI|AHM read buffer invalidate mask}}
+{{rld|0x0d8b0008|32|AHM_RDBI|AHM read data buffer invalidate mask}}
+{{rld|0x0d8b0010|32|AHM_PREFCFG|AHM prefetch configuration}}
{{rld|0x0d8b0020|32|AHM_INTMSK|AHM interrupt mask}}
{{rld|0x0d8b0020|32|AHM_INTMSK|AHM interrupt mask}}
{{rld|0x0d8b0030|32|AHM_INTSTS|AHM interrupt status}}
{{rld|0x0d8b0030|32|AHM_INTSTS|AHM interrupt status}}
−{{rld|0x0d8b0800|32|AHMN_PROTMEM0|AHMN configuration for MEM0 protection}}
+{{rld|0x0d8b0040|32|UNKNOWN|Unknown}}
−{{rld|0x0d8b0804|32|AHMN_PROTMEM1|AHMN configuration for MEM1 protection}}
+{{rld|0x0d8b0044|32|UNKNOWN|Unknown}}
−{{rld|0x0d8b0808|32|AHMN_PROTMEM2|AHMN configuration for MEM2 protection}}
+{{rld|0x0d8b0100...0x0d8b0300|32|AHM_PROTDDR|Each register controls access protection for one page of DDR memory (page size depends on AHM_SECDDR)}}
−{{rld|0x0d8b080c|32|AHMN_RDBI|AHMN read buffer invalidate mask}}
+{{rld|0x0d8b0500...0x0d8b0700|32|AHM_PROTSPL|Each register controls access protection for one page of SPLASH memory (page size depends on AHM_SECSPL)}}
+|}
+== Register Details ==
+= AHMN =
+The Latte hardware contains an enhanced version of AHB_MEM dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).
+{{Infobox MMIO
+| title = AHMN controller
+| arm = Full
+| base = 0x0d8b0800
+| len = 0x800
+| bits = 32
+| ppcirq = ???
+| latteirq = ???
+}}
+== Register List ==
+{{reglist|AHMN controller}}
+{{rld|0x0d8b0800|32|AHMN_SECMEM0|AHMN MEM0 memory security}}
+{{rld|0x0d8b0804|32|AHMN_SECMEM1|AHMN MEM1 memory security}}
+{{rld|0x0d8b0808|32|AHMN_SECMEM2|AHMN MEM2 memory security}}
+{{rld|0x0d8b080c|32|AHMN_RDBI|AHMN read data buffer invalidate mask}}
{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}
{{rld|0x0d8b0820|32|AHMN_INTMSK|AHMN interrupt mask}}
{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}
{{rld|0x0d8b0824|32|AHMN_INTSTS|AHMN interrupt status}}
−{{rld|0x0d8b0840|32|AHMN_UNK|Unknown}}
+{{rld|0x0d8b0840|32|UNKNOWN|Unknown}}
−{{rld|0x0d8b0844|32|AHMN_UNK|Unknown}}
+{{rld|0x0d8b0844|32|UNKNOWN|Unknown}}
{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN transfer status}}
{{rld|0x0d8b0850|32|AHMN_TRFSTS|AHMN transfer status}}
{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}
{{rld|0x0d8b0854|32|AHMN_WORKAROUND|Unknown}}
−{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_MEM0|Each register represents one block of MEM0 memory (block size depends on the AHMN configuration for MEM0)}}
+{{rld|0x0d8b0900...0x0d8b0980|32|AHMN_PROTMEM0|Each register controls access protection for one page of MEM0 memory (page size depends on AHMN_SECMEM0)}}
−{{rld|0x0d8b0a00...0x0d8b0c00|32|AHMN_MEM1|Each register represents one block of MEM1 memory (block size depends on the AHMN configuration for MEM1)}}
+{{rld|0x0d8b0a00...0x0d8b0c00|32|AHMN_PROTMEM1|Each register controls access protection for one page of MEM1 memory (page size depends on AHMN_SECMEM1)}}
−{{rld|0x0d8b0c00...0x0d8b1000|32|AHMN_MEM2|Each register represents one block of MEM2 memory (block size depends on the AHMN configuration for MEM2)}}
+{{rld|0x0d8b0c00...0x0d8b1000|32|AHMN_PROTMEM2|Each register controls access protection for one page of MEM2 memory (page size depends on AHMN_SECMEM2)}}
|}
|}
== Register Details ==
== Register Details ==