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21,367 bytes added , 19:34, 31 December 2024

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= MEM =

{{Infobox MMIO

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| title = MEM controller

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| ppc = Conditional

| arm = Full

| base = 0x0d8b4000

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}}

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~~The Latte hardware implements AMBA (possibly rev 2.0) compliant AHB buses for communication~~ to/~~from the Starbuck's CPU and assorted on-chip hardware blocks (DMA, for example)~~.~~<br>~~

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MEM is the memory controller connected to the [[Hardware/AHM_controller|AHM]] bridge. It is mainly responsible for configuring and controlling DDR memory.

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~~One of such blocks appears to be a customized memory controller that~~ is responsible for ~~several tasks such as~~ DDR ~~configuration, flushing memory to/from the AHB and employing a custom~~ memory ~~protection solution dubbed MEM_BLOCK.<br>~~

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~~This controller appears to be an extension of the one that was previously used on the Wii~~.

== Register List ==

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{{rld|0x0d8b4000|16|MEM_MARR0_START|Memory ~~Protection~~|drs=8}}

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{{rld|0x0d8b4070|16|MEM_ACC_REQCOUNTH|Memory Request Count (ACC) (hi bits)}}

{{rld|0x0d8b4072|16|MEM_ACC_REQCOUNTL|Memory Request Count (ACC) (lo bits)}}

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~~{{rld|0x0d8b42d8|16|MEM_UNK|Unknown}}~~

{{rld|0x0d8b4300|16|MEM_SEQ0_DATA|DDR SEQ0 sequential register's value to read/write}}

{{rld|0x0d8b4302|16|MEM_SEQ0_ADDR|DDR SEQ0 sequential register's address to read/write}}

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{{rld|0x0d8b4406|16|MEM_BLOCK_ERROR_ADDR_LOW|MEM block protection violation's address (low)}}

{{rld|0x0d8b4408|16|MEM_BLOCK_ERROR_ADDR_HIGH|MEM block protection violation's address (high)}}

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~~{{rld|0x0d8b440e|16|MEM_BLOCK_UNK|Unknown}}~~

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~~{{rld|0x0d8b442a|16|MEM_BLOCK_UNK|Unknown}}~~

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~~{{rld|0x0d8b442c|16|MEM_BLOCK_UNK|Unknown}}~~

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~~{{rld|0x0d8b44c4|16|MEM_BLOCK_UNK|Unknown}}~~

{{rld|0x0d8b4472|16|MEM_BLOCK_ERROR_CID|MEM block protection violation's client ID}}

{{rld|0x0d8b4474|16|MEM_BLOCK_ERROR|MEM block protection violation's state}}

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~~{{rld|0x0d8b4494|16|MEM_BLOCK_UNK|Unknown}}~~

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~~{{rld|0x0d8b4492|16|MEM_BLOCK_UNK|Unknown}}~~

|}

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|MODE|MEM1 block translation mode

}}

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= DDR =

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DDR registers. These are indirectly accessed through MEM_DDRREG_ADDR and MEM_DDRREG_DATA. For the most part, these have a direct mirror in MEM's MMIO.

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== Register List ==

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{{rld|0x00000008|16|DDR_MARR_CONTROL|MARR{0-3} permissions}}

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{{rld|0x00000009|16|DDR_CP_BW_DIAL|Bandwidth Dial (Command Processor)}}

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{{rld|0x0000000a|16|DDR_TC_BW_DIAL|Bandwidth Dial (Texture Control)}}

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{{rld|0x0000000b|16|DDR_PE_BW_DIAL|Bandwidth Dial (Pixel Engine)}}

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{{rld|0x0000000d|16|DDR_CPUW_BW_DIAL|Bandwidth Dial (CPU write)}}

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{{rld|0x00000011|16|DDR_INT_ADDRL|MARR interrupt address (lo bits)}}

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{{rld|0x00000012|16|DDR_INT_ADDRH|MARR interrupt address (hi bits)}}

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{{rld|0x00000019|16|DDR_CP_REQCOUNTH|Memory Request Count (Command Processor) (hi bits)}}

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{{rld|0x0000001a|16|DDR_CP_REQCOUNTL|Memory Request Count (Command Processor) (lo bits)}}

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{{rld|0x0000001b|16|DDR_TC_REQCOUNTH|Memory Request Count (Texture Control) (hi bits)}}

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{{rld|0x0000001c|16|DDR_TC_REQCOUNTL|Memory Request Count (Texture Control) (lo bits)}}

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{{rld|0x0000001d|16|DDR_CPUR_REQCOUNTH|Memory Request Count (CPU read) (hi bits)}}

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{{rld|0x0000001e|16|DDR_CPUR_REQCOUNTL|Memory Request Count (CPU read) (lo bits)}}

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{{rld|0x0000001f|16|DDR_CPUW_REQCOUNTH|Memory Request Count (CPU write) (hi bits)}}

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{{rld|0x00000020|16|DDR_CPUW_REQCOUNTL|Memory Request Count (CPU write) (lo bits)}}

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{{rld|0x00000021|16|DDR_DSP_REQCOUNTH|Memory Request Count (DSP) (hi bits)}}

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{{rld|0x00000022|16|DDR_DSP_REQCOUNTL|Memory Request Count (DSP) (lo bits)}}

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{{rld|0x00000023|16|DDR_IO_REQCOUNTH|Memory Request Count (I/O) (hi bits)}}

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{{rld|0x00000024|16|DDR_IO_REQCOUNTL|Memory Request Count (I/O) (lo bits)}}

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{{rld|0x00000025|16|DDR_VI_REQCOUNTH|Memory Request Count (Video Interface) (hi bits)}}

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{{rld|0x00000026|16|DDR_VI_REQCOUNTL|Memory Request Count (Video Interface) (lo bits)}}

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{{rld|0x00000027|16|DDR_PE_REQCOUNTH|Memory Request Count (Pixel Engine) (hi bits)}}

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{{rld|0x00000028|16|DDR_PE_REQCOUNTL|Memory Request Count (Pixel Engine) (lo bits)}}

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{{rld|0x00000029|16|DDR_RF_REQCOUNTH|Memory Request Count (RF) (hi bits)}}

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{{rld|0x0000002a|16|DDR_RF_REQCOUNTL|Memory Request Count (RF) (lo bits)}}

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{{rld|0x0000002b|16|DDR_FI_REQCOUNTH|Memory Request Count (FI) (hi bits)}}

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{{rld|0x0000002c|16|DDR_FI_REQCOUNTL|Memory Request Count (FI) (lo bits)}}

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{{rld|0x00000030|16|DDR_CPUAHMR_REQCOUNTH|Memory Request Count (CPU AHM read) (hi bits)}}

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{{rld|0x00000031|16|DDR_CPUAHMR_REQCOUNTL|Memory Request Count (CPU AHM read) (lo bits)}}

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{{rld|0x00000032|16|DDR_CPUAHMW_REQCOUNTH|Memory Request Count (CPU AHM write) (hi bits)}}

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{{rld|0x00000033|16|DDR_CPUAHMW_REQCOUNTL|Memory Request Count (CPU AHM write) (lo bits)}}

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{{rld|0x00000034|16|DDR_DMAAHMR_REQCOUNTH|Memory Request Count (DMA AHM read) (hi bits)}}

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{{rld|0x00000035|16|DDR_DMAAHMR_REQCOUNTL|Memory Request Count (DMA AHM read) (lo bits)}}

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{{rld|0x00000036|16|DDR_DMAAHMW_REQCOUNTH|Memory Request Count (DMA AHM write) (hi bits)}}

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{{rld|0x00000037|16|DDR_DMAAHMW_REQCOUNTL|Memory Request Count (DMA AHM write) (lo bits)}}

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{{rld|0x00000038|16|DDR_ACC_REQCOUNTH|Memory Request Count (ACC) (hi bits)}}

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{{rld|0x00000039|16|DDR_ACC_REQCOUNTL|Memory Request Count (ACC) (lo bits)}}

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{{rld|0x00000103|16|DDR_PROT_SPL_BASE|SPL protection base address}}

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{{rld|0x00000104|16|DDR_PROT_SPL_END|SPL protection end address}}

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{{rld|0x00000106|16|DDR_PROT_DDR_BASE|DDR protection base address}}

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{{rld|0x00000107|16|DDR_PROT_DDR_END|DDR protection end address}}

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{{rld|0x00000115|16|DDR_AHMFLUSH_ACK|AHM flush request acknowledgment}}

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{{rld|0x00000162|16|DDR_SEQ_DATA|DDR SEQ register's value to read/write}}

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{{rld|0x00000163|16|DDR_SEQ_ADDR|DDR SEQ register's address to read/write}}

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{{rld|0x00000164|16|DDR_BIST_DATA|DDR BIST register's address to read/write}}

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{{rld|0x00000165|16|DDR_BIST_ADDR|DDR BIST register's address to read/write}}

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{{rld|0x00000166|16|DDR_EDRAM_REFRESH_CTRL|EDRAM refresh settings}}

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{{rld|0x00000180|16|DDR_SEQ0_DATA|DDR SEQ0 sequential register's value to read/write}}

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{{rld|0x00000181|16|DDR_SEQ0_ADDR|DDR SEQ0 sequential register's address to read/write}}

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{{rld|0x00000200|16|DDR_BLOCK_MEM0_CFG|MEM block protection configuration for MEM0}}

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{{rld|0x00000201|16|DDR_BLOCK_MEM1_CFG|MEM block protection configuration for MEM1}}

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{{rld|0x00000202|16|DDR_BLOCK_MEM2_CFG|MEM block protection configuration for MEM2}}

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{{rld|0x00000203|16|DDR_BLOCK_ERROR_ADDR_LOW|MEM block protection violation's address (low)}}

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{{rld|0x00000204|16|DDR_BLOCK_ERROR_ADDR_HIGH|MEM block protection violation's address (high)}}

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{{rld|0x00000239|16|DDR_BLOCK_ERROR_CID|MEM block protection violation's client ID}}

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{{rld|0x0000023a|16|DDR_BLOCK_ERROR|MEM block protection violation's state}}

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|}

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== Register Details ==

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= SEQ =

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DDR sequencer registers. These are indirectly accessed through MEM_SEQ_ADDR/DDR_SEQ_ADDR and MEM_SEQ_DATA/DDR_SEQ_DATA.

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== Register List ==

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|}

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== Register Details ==

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= BIST =

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DDR built-in self-test registers. These are indirectly accessed through MEM_BIST_ADDR/DDR_BIST_ADDR and MEM_BIST_DATA/DDR_BIST_DATA.

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== Register List ==

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|}

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== Register Details ==

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= DPERF =

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DDR performance registers. These are indirectly accessed through MEM_PERF/DDR_PERF and MEM_PERF_READ/DDR_PERF_READ.

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== Register List ==

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|}

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== Register Details ==

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Changes

Hardware/Memory controller (view source)

Revision as of 19:34, 31 December 2024