Line 16:
Line 16:
- Reset the EXI channel.
- Reset the EXI channel.
−
===RTC offsets===
+
== Registers ==
The RTC exposes a few control registers and SRAM memory access in the form of EXI offsets, which can be accessed to read and write 32-bit values or perform DMA operations (in the case of SRAM).
The RTC exposes a few control registers and SRAM memory access in the form of EXI offsets, which can be accessed to read and write 32-bit values or perform DMA operations (in the case of SRAM).
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
{| style="border: 1px solid #bbb; border-collapse: collapse; background-color: #eef; padding: 0.2em 0.2em 0.2em 0.2em;" border="1" cellpadding="2"
|- style="background-color: #ddd;"
|- style="background-color: #ddd;"
−
! Name
! Offset
! Offset
! Description
! Description
|-
|-
−
| RTC_COUNTER || 0x20000000 || Contains the counting time intervals in seconds
+
| 0x20000000 || [[#RTC_COUNTER|RTC_COUNTER]]
|-
|-
−
| RTC_SRAM || 0x20000100 || Battery backed memory
+
| 0x20000100 || RTC_SRAM0
−
The SRAM has a total size of 64 bytes, starting at offset 0x20000100 and ending at offset 0x20001000.
−
Therefore, each word is located at (0x20000100 + 0x100 * i) with (i < 0x10).
−
On Wii U mode (recent firmware versions only), this memory is used to store IOSU kernel panic strings.
|-
|-
−
| RTC_SNAPSHOT || 0x20400000 || Contains a snapshot of RTC_COUNTER
+
| 0x20000200 || RTC_SRAM1
|-
|-
−
| ONTMR_SET || 0x21000000 || Contains the value set for the ON timer
+
| 0x20000300 || RTC_SRAM2
−
The value set here is masked with 0x3FFFFFFF and represents time intervals in seconds.
−
The following flags can be set on the value's upper bits:
−
0x80000000 (ONTMR_EN): Enable/disable the ON timer.
−
0x40000000 (PONTMR_DTCT): Unknown.
|-
|-
−
| OFFTMR_SET || 0x21000100 || Contains the value set for the OFF timer
+
| 0x20000400 || RTC_SRAM3
−
The value set here is masked with 0x3FFFFFFF and represents time intervals in seconds.
−
The following flags can be set on the value's upper bits:
−
0x80000000 (OFFTMR_EN): Enable/disable the OFF timer.
−
0x40000000 (POFFTMR_DTCT): Unknown.
|-
|-
−
| RTC_TEST0 || 0x21000400 || Always 0x03030303 after power on (test pattern)
+
| 0x20000500 || RTC_SRAM4
|-
|-
−
| RTC_TEST1 || 0x21000500 || Always 0x03030303 after power on (test pattern)
+
| 0x20000600 || RTC_SRAM5
|-
|-
−
| RTC_TEST2 || 0x21000600 || Always 0x03030303 after power on (test pattern)
+
| 0x20000700 || RTC_SRAM6
|-
|-
−
| RTC_TEST3 || 0x21000700 || Always 0x03030303 after power on (test pattern)
+
| 0x20000800 || RTC_SRAM7
|-
|-
−
| RTC_CONTROL0 || 0x21000C00 || RTC control register 0
+
| 0x20000900 || RTC_SRAM8
−
The last byte stored here (mask == 0x000000FF) is always RTC_REVISION (0x00 or 0x01).
−
The following flags can be set here:
−
0x04000000 (POFFLG_FPOFF): Set upon a forced power off.
−
0x02000000 (POFFLG_4S): Set upon a 4 second power button press.
−
0x01000000 (POFFLG_TMR): Set upon a OFF timer power off.
−
0x00020000 (PONFLG_SYS): Set upon a system power event.
−
0x00010000 (PONLG_TMR): Set upon a ON timer power on.
−
0x00000800 (UNSTBL_PWR): Unknown. boot0 checks this before launching a recovery boot1 image.
−
0x00000200 (LOW_BATT): Set when the CMOS battery is worn off.
−
0x00000100 (CANARY): Used by IOS-ACP when handling the rtcflag0.dat and rtcflag1.dat files.
|-
|-
−
| RTC_CONTROL1 || 0x21000D00 || RTC control register 1
+
| 0x20000A00 || RTC_SRAM9
−
The following flags can be set here:
−
0x00010000 (POFF_EXE): Setting this flag executes a power off event.
−
0x00000400 (DEVPWR_EN or DEVPWR_SYNC): If set, this flag is referred to as DEVPWR_EN (device power enabled?).
−
If not set, this flag is referred to as DEVPWR_SYNC (device power sync?).
−
0x00000100 (SLEEP_EN): Setting this flag puts the RTC in sleep mode (used in standby mode).
−
0x00000008 (FPOFF_MODE): This flag defines the forced power off event mode.
−
0x00000004 (CLKOUT_EN): This flag enables/disables the CLKOUT pin.
−
0x00000001 (4COUNT_EN): This flag enables/disables the 4 second power button press functionality.
|-
|-
+
| 0x20000B00 || RTC_SRAMA
+
|-
+
| 0x20000C00 || RTC_SRAMB
+
|-
+
| 0x20000D00 || RTC_SRAMC
+
|-
+
| 0x20000E00 || RTC_SRAMD
+
|-
+
| 0x20000F00 || RTC_SRAME
+
|-
+
| 0x20001000 || RTC_SRAMF
+
|-
+
| 0x20400000 || [[#RTC_SNAPSHOT|RTC_SNAPSHOT]]
+
|-
+
| 0x21000000 || [[#RTC_ONTMR|RTC_ONTMR]]
+
|-
+
| 0x21000100 || [[#RTC_OFFTMR|RTC_OFFTMR]]
+
|-
+
| 0x21000400 || RTC_COMPATSET
+
|-
+
| 0x21000800 || RTC_COMPATINT
+
|-
+
| 0x21000C00 || [[#RTC_CONTROL0|RTC_CONTROL0]]
+
|-
+
| 0x21000D00 || [[#RTC_CONTROL1|RTC_CONTROL1]]
+
|-
+
| 0x21000E00 || RTC_CONTROL2
+
|-
+
| 0x21000F00 || RTC_CONTROL3
+
|-
+
| 0x21001000 || RTC_SCRATCH0
+
|-
+
| 0x21001100 || RTC_SCRATCH1
+
|-
+
| 0x21001200 || RTC_SCRATCH2
+
|-
+
| 0x21001300 || RTC_SCRATCH3
+
|-
+
| 0x21001800 || RTC_NORMALINT
+
|}
+
+
=== RTC_COUNTER ===
+
Counting time intervals in seconds.
+
+
=== RTC_SNAPSHOT ===
+
Snapshot of RTC_COUNTER.
+
+
=== RTC_ONTMR ===
+
{| class="wikitable"
+
|-
+
! Bits
+
! Description
+
|-
+
| 0-29
+
| ONTMR_SET
+
|-
+
| 30
+
| PONTMR_DTCT
+
|-
+
| 31
+
| ONTMR_EN
+
|}
+
+
=== RTC_OFFTMR ===
+
{| class="wikitable"
+
|-
+
! Bits
+
! Description
+
|-
+
| 0-29
+
| OFFTMR_SET
+
|-
+
| 30
+
| POFFTMR_DTCT
+
|-
+
| 31
+
| OFFTMR_EN
+
|}
+
+
=== RTC_CONTROL0 ===
+
{| class="wikitable"
+
|-
+
! Bits
+
! Description
+
|-
+
| 0-7
+
| RTC_REVISION
+
|-
+
| 8
+
| CANARY
+
|-
+
| 9
+
| LOW_BATT
+
|-
+
| 10
+
|
+
|-
+
| 11
+
| UNSTBL_PWR
+
|-
+
| 12-15
+
|
+
|-
+
| 16
+
| PONLG_TMR
+
|-
+
| 17
+
| PONFLG_SYS
+
|-
+
| 18-23
+
|
+
|-
+
| 24
+
| POFFLG_TMR
+
|-
+
| 25
+
| POFFLG_4S
+
|-
+
| 26
+
| POFFLG_FPOFF
+
|-
+
| 27-31
+
|
+
|}
+
+
=== RTC_CONTROL1 ===
+
{| class="wikitable"
+
|-
+
! Bits
+
! Description
+
|-
+
| 0
+
| 4COUNT_EN
+
|-
+
| 1
+
|
+
|-
+
| 2
+
| CLKOUT_EN
+
|-
+
| 3
+
| FPOFF_MODE
+
|-
+
| 4-7
+
|
+
|-
+
| 8
+
| SLEEP_EN
+
|-
+
| 9
+
|
+
|-
+
| 10
+
| DEVPWR_EN
+
|-
+
| 11-15
+
|
+
|-
+
| 16
+
| POFF_EXE
+
|-
+
| 17-31
+
|
|}
|}