Hardware/Legacy

In order to provide backwards compatibility, the Latte still maps several legacy hardware registers for the vWii to see.
These legacy entries are set and maintained by the IOS-BSP module in the IOSU.

Drive Interface

Drive Interface
Access
Espresso	Conditional
Starbuck	Full
Registers
Base	0x0d806000
Length	0x400
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	???
Latte	???

Register List

Drive Interface
Address	Bits	Name	Description
0x0d806000	32	DI2SATA_SR	DI status register
0x0d806004	32	DI2SATA_CVR	DI cover register (status2)
0x0d806008	32	DI2SATA_CMDBUF0	DI command buffer 0
0x0d80600c	32	DI2SATA_CMDBUF1	DI command buffer 1
0x0d806010	32	DI2SATA_CMDBUF2	DI command buffer 2
0x0d806014	32	DI2SATA_MAR	DI DMA memory address register
0x0d806018	32	DI2SATA_LENGTH	DI DMA transfer length register
0x0d80601c	32	DI2SATA_CR	Unknown
0x0d806020	32	DI2SATA_IMMBUF	DI immediate data buffer
0x0d806024	32	DI2SATA_CONFIG	DI configuration register
0x0d806028	32	DI2SATA_COMPAT	DI compat mode

Serial Interface

Serial Interface
Access
Espresso	Full
Starbuck	Full
Registers
Base	0x0d806400
Length	0x400
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	???
Latte	???

External Interface

External Interface
Access
Espresso	Partial
Starbuck	Full
Registers
Base	0x0d806800
Length	0x400
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	???
Latte	???

For compatibility purposes, the Wii U implements the External Interface similarly to the GameCube and the Wii. On a regular retail Wii U, the RTC is the only device registered on the EXI bus (channel 0, device 1). An additional device called NESCAFE (part of the debug CORTADO package) was presumably used in the past for debugging purposes and used to sit on channel 0 as device 2.

This bus is accessible externally via the following test points:

• TP101 - CLK
• TP176 - MISO (Device out, Wii U in)
• Test point between TP100 and TP176 - MOSI (Device in, Wii U out)

Register List

EXI Interface
Address	Bits	Name	Description
0x0d806800	32	EXI0_CSR	EXI Channel 0 Parameter Register
0x0d806804	32	EXI0_MAR	EXI Channel 0 DMA Start Address
0x0d806808	32	EXI0_LENGTH	EXI Channel 0 DMA Transfer Length
0x0d80680c	32	EXI0_CR	EXI Channel 0 Control Register
0x0d806810	32	EXI0_DATA	EXI Channel 0 Immediate Data
0x0d806814	32	EXI1_CSR	EXI Channel 1 Parameter Register
0x0d806818	32	EXI1_MAR	EXI Channel 1 DMA Start Address
0x0d80681c	32	EXI1_LENGTH	EXI Channel 1 DMA Transfer Length
0x0d806820	32	EXI1_CR	EXI Channel 1 Control Register
0x0d806824	32	EXI1_DATA	EXI Channel 1 Immediate Data
0x0d806828	32	EXI2_CSR	EXI Channel 2 Parameter Register
0x0d80682c	32	EXI2_MAR	EXI Channel 2 DMA Start Address
0x0d806830	32	EXI2_LENGTH	EXI Channel 2 DMA Transfer Length
0x0d806834	32	EXI2_CR	EXI Channel 2 Control Register
0x0d806838	32	EXI2_DATA	EXI Channel 2 Immediate Data

Register Details

EXIx_CR (0x0d80680c/0x0d806820/0x0d806834)
	310
Access	W

EXIx_DATA (0x0d806810/0x0d806824/0x0d806838)
	310
Access	R/W

When IOSU sends data to the device, it:

• Writes the data into EXI_DATA
• Writes 0x35 into EXI_CR
• Waits for IRQ #20

When IOSU reads data from the device, it:

• Writes 0x31 into EXI_CR
• Waits for IRQ #20
• Reads the data from EXI_DATA

Audio Interface

Audio Interface
Access
Espresso	Full
Starbuck	Full
Registers
Base	0x0d806c00
Length	0x400
Access size	32 bits
Byte order	Big Endian
IRQs
Espresso	???
Latte	???