Hardware/Memory controller
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MEM
| MEM controller | |
| Access | |
|---|---|
| Espresso | Conditional |
| Starbuck | Full |
| Registers | |
| Base | 0x0d8b4000 |
| Length | 0xc000 |
| Access size | 16 bits |
| Byte order | Big Endian |
| IRQs | |
| Espresso | ??? |
| Latte | ??? |
MEM is the memory controller connected to the AHM bridge. It is mainly responsible for configuring and controlling DDR memory.
Register List
| Memory controller | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x0d8b4000 | 16 | MEM_MARR0_START | Memory protection |
| 0x0d8b4002 | 16 | MEM_MARR0_END | |
| 0x0d8b4004 | 16 | MEM_MARR1_START | |
| 0x0d8b4006 | 16 | MEM_MARR1_END | |
| 0x0d8b4008 | 16 | MEM_MARR2_START | |
| 0x0d8b400a | 16 | MEM_MARR2_END | |
| 0x0d8b400c | 16 | MEM_MARR3_START | |
| 0x0d8b400e | 16 | MEM_MARR3_END | |
| 0x0d8b4010 | 16 | MEM_MARR_CONTROL | MARR{0-3} permissions |
| 0x0d8b4012 | 16 | MEM_CP_BW_DIAL | Bandwidth Dial (Command Processor) |
| 0x0d8b4014 | 16 | MEM_TC_BW_DIAL | Bandwidth Dial (Texture Control) |
| 0x0d8b4016 | 16 | MEM_PE_BW_DIAL | Bandwidth Dial (Pixel Engine) |
| 0x0d8b4018 | 16 | MEM_CPUR_BW_DIAL | Bandwidth Dial (CPU read) |
| 0x0d8b401a | 16 | MEM_CPUW_BW_DIAL | Bandwidth Dial (CPU write) |
| 0x0d8b401c | 16 | MEM_INT_ENBL | MARR interrupt enable |
| 0x0d8b401e | 16 | MEM_INT_STAT | MARR interrupt status |
| 0x0d8b4020 | 16 | MEM_INT_CLR | MARR interrupt clear/mask (?) |
| 0x0d8b4022 | 16 | MEM_INT_ADDRL | MARR interrupt address (lo bits) |
| 0x0d8b4024 | 16 | MEM_INT_ADDRH | MARR interrupt address (hi bits) |
| 0x0d8b4026 | 16 | MEM_REFRESH | Memory refresh |
| 0x0d8b4028 | 16 | MEM_CONFIG | Memory configuration |
| 0x0d8b402a | 16 | MEM_LATENCY | Memory latency |
| 0x0d8b402c | 16 | MEM_RDTORD | Memory read to read |
| 0x0d8b402e | 16 | MEM_RDTOWR | Memory read to write |
| 0x0d8b4030 | 16 | MEM_WRTORD | Memory write to read |
| 0x0d8b4032 | 16 | MEM_CP_REQCOUNTH | Memory Request Count (Command Processor) (hi bits) |
| 0x0d8b4034 | 16 | MEM_CP_REQCOUNTL | Memory Request Count (Command Processor) (lo bits) |
| 0x0d8b4036 | 16 | MEM_TC_REQCOUNTH | Memory Request Count (Texture Control) (hi bits) |
| 0x0d8b4038 | 16 | MEM_TC_REQCOUNTL | Memory Request Count (Texture Control) (lo bits) |
| 0x0d8b403a | 16 | MEM_CPUR_REQCOUNTH | Memory Request Count (CPU read) (hi bits) |
| 0x0d8b403c | 16 | MEM_CPUR_REQCOUNTL | Memory Request Count (CPU read) (lo bits) |
| 0x0d8b403e | 16 | MEM_CPUW_REQCOUNTH | Memory Request Count (CPU write) (hi bits) |
| 0x0d8b4040 | 16 | MEM_CPUW_REQCOUNTL | Memory Request Count (CPU write) (lo bits) |
| 0x0d8b4042 | 16 | MEM_DSP_REQCOUNTH | Memory Request Count (DSP) (hi bits) |
| 0x0d8b4044 | 16 | MEM_DSP_REQCOUNTL | Memory Request Count (DSP) (lo bits) |
| 0x0d8b4046 | 16 | MEM_IO_REQCOUNTH | Memory Request Count (I/O) (hi bits) |
| 0x0d8b4048 | 16 | MEM_IO_REQCOUNTL | Memory Request Count (I/O) (lo bits) |
| 0x0d8b404a | 16 | MEM_VI_REQCOUNTH | Memory Request Count (Video Interface) (hi bits) |
| 0x0d8b404c | 16 | MEM_VI_REQCOUNTL | Memory Request Count (Video Interface) (lo bits) |
| 0x0d8b404e | 16 | MEM_PE_REQCOUNTH | Memory Request Count (Pixel Engine) (hi bits) |
| 0x0d8b4050 | 16 | MEM_PE_REQCOUNTL | Memory Request Count (Pixel Engine) (lo bits) |
| 0x0d8b4052 | 16 | MEM_RF_REQCOUNTH | Memory Request Count (RF) (hi bits) |
| 0x0d8b4054 | 16 | MEM_RF_REQCOUNTL | Memory Request Count (RF) (lo bits) |
| 0x0d8b4056 | 16 | MEM_FI_REQCOUNTH | Memory Request Count (FI) (hi bits) |
| 0x0d8b4058 | 16 | MEM_FI_REQCOUNTL | Memory Request Count (FI) (lo bits) |
| 0x0d8b405a | 16 | MEM_DRV_STRENGTH | Unknown |
| 0x0d8b405c | 16 | MEM_REFRSH_THHD | Unknown |
| 0x0d8b4060 | 16 | MEM_CPUAHMR_REQCOUNTH | Memory Request Count (CPU AHM read) (hi bits) |
| 0x0d8b4062 | 16 | MEM_CPUAHMR_REQCOUNTL | Memory Request Count (CPU AHM read) (lo bits) |
| 0x0d8b4064 | 16 | MEM_CPUAHMW_REQCOUNTH | Memory Request Count (CPU AHM write) (hi bits) |
| 0x0d8b4066 | 16 | MEM_CPUAHMW_REQCOUNTL | Memory Request Count (CPU AHM write) (lo bits) |
| 0x0d8b4068 | 16 | MEM_DMAAHMR_REQCOUNTH | Memory Request Count (DMA AHM read) (hi bits) |
| 0x0d8b406a | 16 | MEM_DMAAHMR_REQCOUNTL | Memory Request Count (DMA AHM read) (lo bits) |
| 0x0d8b406c | 16 | MEM_DMAAHMW_REQCOUNTH | Memory Request Count (DMA AHM write) (hi bits) |
| 0x0d8b406e | 16 | MEM_DMAAHMW_REQCOUNTL | Memory Request Count (DMA AHM write) (lo bits) |
| 0x0d8b4070 | 16 | MEM_ACC_REQCOUNTH | Memory Request Count (ACC) (hi bits) |
| 0x0d8b4072 | 16 | MEM_ACC_REQCOUNTL | Memory Request Count (ACC) (lo bits) |
| 0x0d8b4074 | 16 | MEM_DDRREG_ADDR | DDR memory register offset |
| 0x0d8b4076 | 16 | MEM_DDRREG_DATA | DDR memory register data |
| 0x0d8b4078 | 16 | MEM_DRV_PSTRENGTH | Unknown |
| 0x0d8b4200 | 16 | MEM_COMPAT | Unknown |
| 0x0d8b4202 | 16 | MEM_PROT_REG | Unknown |
| 0x0d8b4204 | 16 | MEM_PROT_SPL | SPL protection enable/disable |
| 0x0d8b4206 | 16 | MEM_PROT_SPL_BASE | SPL protection base address |
| 0x0d8b4208 | 16 | MEM_PROT_SPL_END | SPL protection end address |
| 0x0d8b420a | 16 | MEM_PROT_DDR | DDR protection enable/disable |
| 0x0d8b420c | 16 | MEM_PROT_DDR_BASE | DDR protection base address |
| 0x0d8b420e | 16 | MEM_PROT_DDR_END | DDR protection end address |
| 0x0d8b4210 | 16 | MEM_COLSEL | Unknown |
| 0x0d8b4212 | 16 | MEM_ROWSEL | Unknown |
| 0x0d8b4214 | 16 | MEM_BANKSEL | Unknown |
| 0x0d8b4216 | 16 | MEM_RANKSEL | Unknown |
| 0x0d8b4218 | 16 | MEM_COLMSK | Unknown |
| 0x0d8b421a | 16 | MEM_ROWMSK | Unknown |
| 0x0d8b421c | 16 | MEM_BANKMSK | Unknown |
| 0x0d8b421e | 16 | MEM_PROT_SPL_ERR | SPL protection error |
| 0x0d8b4220 | 16 | MEM_PROT_DDR_ERR | DDR protection error |
| 0x0d8b4222 | 16 | MEM_PROT_SPL_MSK | SPL protection mask |
| 0x0d8b4224 | 16 | MEM_PROT_DDR_MSK | DDR protection mask |
| 0x0d8b4226 | 16 | MEM_RFSH | Unknown |
| 0x0d8b4228 | 16 | MEM_AHMFLUSH | AHB flush request |
| 0x0d8b422a | 16 | MEM_AHMFLUSH_ACK | AHB flush request acknowledgment |
| 0x0d8b4268 | 16 | MEM_SEQRD_HWM | Unknown |
| 0x0d8b426a | 16 | MEM_SEQWR_HWM | Unknown |
| 0x0d8b426c | 16 | MEM_SEQCMD_HWM | Unknown |
| 0x0d8b426e | 16 | MEM_CPUAHM_WR_T | Unknown |
| 0x0d8b4270 | 16 | MEM_DMAAHM_WR_T | Unknown |
| 0x0d8b4272 | 16 | MEM_DMAAHM0_WR_T | Unknown |
| 0x0d8b4274 | 16 | MEM_DMAAHM1_WR_T | Unknown |
| 0x0d8b4276 | 16 | MEM_PI_WR_T | Unknown |
| 0x0d8b4278 | 16 | MEM_PE_WR_T | Unknown |
| 0x0d8b427a | 16 | MEM_IO_WR_T | Unknown |
| 0x0d8b427c | 16 | MEM_DSP_WR_T | Unknown |
| 0x0d8b427e | 16 | MEM_ACC_WR_T | Unknown |
| 0x0d8b4280 | 16 | MEM_ARB_MAXWR | Unknown |
| 0x0d8b4282 | 16 | MEM_ARB_MINRD | Unknown |
| 0x0d8b4284 | 16 | MEM_PROF_CPUAHM | Unknown |
| 0x0d8b4286 | 16 | MEM_PROF_CPUAHM0 | Unknown |
| 0x0d8b4288 | 16 | MEM_PROF_DMAAHM | Unknown |
| 0x0d8b428a | 16 | MEM_PROF_DMAAHM0 | Unknown |
| 0x0d8b428c | 16 | MEM_PROF_DMAAHM1 | Unknown |
| 0x0d8b428e | 16 | MEM_PROF_PI | Unknown |
| 0x0d8b4290 | 16 | MEM_PROF_VI | Unknown |
| 0x0d8b4292 | 16 | MEM_PROF_IO | Unknown |
| 0x0d8b4294 | 16 | MEM_PROF_DSP | Unknown |
| 0x0d8b4296 | 16 | MEM_PROF_TC | Unknown |
| 0x0d8b4298 | 16 | MEM_PROF_CP | Unknown |
| 0x0d8b429a | 16 | MEM_PROF_ACC | Unknown |
| 0x0d8b429c | 16 | MEM_RDPR_CPUAHM | Unknown |
| 0x0d8b429e | 16 | MEM_RDPR_CPUAHM0 | Unknown |
| 0x0d8b42a0 | 16 | MEM_RDPR_DMAAHM | Unknown |
| 0x0d8b42a2 | 16 | MEM_RDPR_DMAAHM0 | Unknown |
| 0x0d8b42a4 | 16 | MEM_RDPR_DMAAHM1 | Unknown |
| 0x0d8b42a6 | 16 | MEM_RDPR_PI | Unknown |
| 0x0d8b42a8 | 16 | MEM_RDPR_VI | Unknown |
| 0x0d8b42aa | 16 | MEM_RDPR_IO | Unknown |
| 0x0d8b42ac | 16 | MEM_RDPR_DSP | Unknown |
| 0x0d8b42ae | 16 | MEM_RDPR_TC | Unknown |
| 0x0d8b42b0 | 16 | MEM_RDPR_CP | Unknown |
| 0x0d8b42b2 | 16 | MEM_RDPR_ACC | Unknown |
| 0x0d8b42b4 | 16 | MEM_ARB_MAXRD | Unknown |
| 0x0d8b42b6 | 16 | MEM_ARB_MISC | Unknown |
| 0x0d8b42b8 | 16 | MEM_ARAM_EMUL | Unknown |
| 0x0d8b42ba | 16 | MEM_WRMUX | Unknown |
| 0x0d8b42bc | 16 | MEM_PERF | Unknown |
| 0x0d8b42be | 16 | MEM_PERF_READ | Unknown |
| 0x0d8b42c0 | 16 | MEM_ARB_EXADDR | Unknown |
| 0x0d8b42c2 | 16 | MEM_ARB_EXCMD | Unknown |
| 0x0d8b42c4 | 16 | MEM_SEQ_DATA | DDR SEQ register's value to read/write |
| 0x0d8b42c6 | 16 | MEM_SEQ_ADDR | DDR SEQ register's address to read/write |
| 0x0d8b42c8 | 16 | MEM_BIST_DATA | DDR BIST register's address to read/write |
| 0x0d8b42ca | 16 | MEM_BIST_ADDR | DDR BIST register's address to read/write |
| 0x0d8b42cc | 16 | MEM_EDRAM_REFRESH_CTRL | EDRAM refresh settings |
| 0x0d8b42ce | 16 | MEM_EDRAM_REFRESH_VAL | EDRAM refresh value |
| 0x0d8b42d4 | 16 | MEM_MEM1_COMPAT_MODE | Unknown |
| 0x0d8b42d6 | 16 | MEM_CAFE_DDR_RANGE_TOP | Unknown |
| 0x0d8b4300 | 16 | MEM_SEQ0_DATA | DDR SEQ0 sequential register's value to read/write |
| 0x0d8b4302 | 16 | MEM_SEQ0_ADDR | DDR SEQ0 sequential register's address to read/write |
| 0x0d8b4400 | 16 | MEM_BLOCK_MEM0_CFG | MEM block protection configuration for MEM0 |
| 0x0d8b4402 | 16 | MEM_BLOCK_MEM1_CFG | MEM block protection configuration for MEM1 |
| 0x0d8b4404 | 16 | MEM_BLOCK_MEM2_CFG | MEM block protection configuration for MEM2 |
| 0x0d8b4406 | 16 | MEM_BLOCK_ERROR_ADDR_LOW | MEM block protection violation's address (low) |
| 0x0d8b4408 | 16 | MEM_BLOCK_ERROR_ADDR_HIGH | MEM block protection violation's address (high) |
| 0x0d8b4472 | 16 | MEM_BLOCK_ERROR_CID | MEM block protection violation's client ID |
| 0x0d8b4474 | 16 | MEM_BLOCK_ERROR | MEM block protection violation's state |
| 0x0d8b464a | 16 | MEM_GPU_ENDIANNESS | GPU endianness control |
Register Details
| MEM_MEM1_COMPAT_MODE (0x0d8b42d4) | ||||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | U | R/W | ||||||||||||||
| Field | MODE | |||||||||||||||
This register modifies the translation of addresses to MEM1 locations in blocks of 0x100 bytes. It is modified by cafe2wii while entering vWii mode.
The 25 bits of a MEM1 address can be split into 8 least significant bits of offset, left unmodified by the translation process, and 17 bits representing the block number.
In mode 0, no translation is applied. This mode is normally used in WiiU mode and during boot.
In mode 1, the 4 least significant bits of the block number are rotated left by 3 bits.
In mode 2, the 11 least significant bits of the block number are rotated left by 3 bits.
In mode 3, all 17 bits of the block number are rotated left by 3 bits. This mode is normally used in vWii mode.
| Field | Description |
| MODE | MEM1 block translation mode |
DDR
DDR registers. These are indirectly accessed through MEM_DDRREG_ADDR and MEM_DDRREG_DATA. For the most part, these have a direct mirror in MEM's MMIO.
Register List
| DDR controller | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x00000000 | 16 | DDR_MARR0_START | Memory protection |
| 0x00000001 | 16 | DDR_MARR0_END | |
| 0x00000002 | 16 | DDR_MARR1_START | |
| 0x00000003 | 16 | DDR_MARR1_END | |
| 0x00000004 | 16 | DDR_MARR2_START | |
| 0x00000005 | 16 | DDR_MARR2_END | |
| 0x00000006 | 16 | DDR_MARR3_START | |
| 0x00000007 | 16 | DDR_MARR3_END | |
| 0x00000008 | 16 | DDR_MARR_CONTROL | MARR{0-3} permissions |
| 0x00000009 | 16 | DDR_CP_BW_DIAL | Bandwidth Dial (Command Processor) |
| 0x0000000a | 16 | DDR_TC_BW_DIAL | Bandwidth Dial (Texture Control) |
| 0x0000000b | 16 | DDR_PE_BW_DIAL | Bandwidth Dial (Pixel Engine) |
| 0x0000000c | 16 | DDR_CPUR_BW_DIAL | Bandwidth Dial (CPU read) |
| 0x0000000d | 16 | DDR_CPUW_BW_DIAL | Bandwidth Dial (CPU write) |
| 0x0000000e | 16 | DDR_INT_ENBL | MARR interrupt enable |
| 0x0000000f | 16 | DDR_INT_STAT | MARR interrupt status |
| 0x00000010 | 16 | DDR_INT_CLR | MARR interrupt clear/mask (?) |
| 0x00000011 | 16 | DDR_INT_ADDRL | MARR interrupt address (lo bits) |
| 0x00000012 | 16 | DDR_INT_ADDRH | MARR interrupt address (hi bits) |
| 0x00000013 | 16 | DDR_REFRESH | Memory refresh |
| 0x00000014 | 16 | DDR_CONFIG | Memory configuration |
| 0x00000015 | 16 | DDR_LATENCY | Memory latency |
| 0x00000016 | 16 | DDR_RDTORD | Memory read to read |
| 0x00000017 | 16 | DDR_RDTOWR | Memory read to write |
| 0x00000018 | 16 | DDR_WRTORD | Memory write to read |
| 0x00000019 | 16 | DDR_CP_REQCOUNTH | Memory Request Count (Command Processor) (hi bits) |
| 0x0000001a | 16 | DDR_CP_REQCOUNTL | Memory Request Count (Command Processor) (lo bits) |
| 0x0000001b | 16 | DDR_TC_REQCOUNTH | Memory Request Count (Texture Control) (hi bits) |
| 0x0000001c | 16 | DDR_TC_REQCOUNTL | Memory Request Count (Texture Control) (lo bits) |
| 0x0000001d | 16 | DDR_CPUR_REQCOUNTH | Memory Request Count (CPU read) (hi bits) |
| 0x0000001e | 16 | DDR_CPUR_REQCOUNTL | Memory Request Count (CPU read) (lo bits) |
| 0x0000001f | 16 | DDR_CPUW_REQCOUNTH | Memory Request Count (CPU write) (hi bits) |
| 0x00000020 | 16 | DDR_CPUW_REQCOUNTL | Memory Request Count (CPU write) (lo bits) |
| 0x00000021 | 16 | DDR_DSP_REQCOUNTH | Memory Request Count (DSP) (hi bits) |
| 0x00000022 | 16 | DDR_DSP_REQCOUNTL | Memory Request Count (DSP) (lo bits) |
| 0x00000023 | 16 | DDR_IO_REQCOUNTH | Memory Request Count (I/O) (hi bits) |
| 0x00000024 | 16 | DDR_IO_REQCOUNTL | Memory Request Count (I/O) (lo bits) |
| 0x00000025 | 16 | DDR_VI_REQCOUNTH | Memory Request Count (Video Interface) (hi bits) |
| 0x00000026 | 16 | DDR_VI_REQCOUNTL | Memory Request Count (Video Interface) (lo bits) |
| 0x00000027 | 16 | DDR_PE_REQCOUNTH | Memory Request Count (Pixel Engine) (hi bits) |
| 0x00000028 | 16 | DDR_PE_REQCOUNTL | Memory Request Count (Pixel Engine) (lo bits) |
| 0x00000029 | 16 | DDR_RF_REQCOUNTH | Memory Request Count (RF) (hi bits) |
| 0x0000002a | 16 | DDR_RF_REQCOUNTL | Memory Request Count (RF) (lo bits) |
| 0x0000002b | 16 | DDR_FI_REQCOUNTH | Memory Request Count (FI) (hi bits) |
| 0x0000002c | 16 | DDR_FI_REQCOUNTL | Memory Request Count (FI) (lo bits) |
| 0x0000002d | 16 | DDR_DRV_STRENGTH | Unknown |
| 0x0000002e | 16 | DDR_REFRSH_THHD | Unknown |
| 0x00000030 | 16 | DDR_CPUAHMR_REQCOUNTH | Memory Request Count (CPU AHM read) (hi bits) |
| 0x00000031 | 16 | DDR_CPUAHMR_REQCOUNTL | Memory Request Count (CPU AHM read) (lo bits) |
| 0x00000032 | 16 | DDR_CPUAHMW_REQCOUNTH | Memory Request Count (CPU AHM write) (hi bits) |
| 0x00000033 | 16 | DDR_CPUAHMW_REQCOUNTL | Memory Request Count (CPU AHM write) (lo bits) |
| 0x00000034 | 16 | DDR_DMAAHMR_REQCOUNTH | Memory Request Count (DMA AHM read) (hi bits) |
| 0x00000035 | 16 | DDR_DMAAHMR_REQCOUNTL | Memory Request Count (DMA AHM read) (lo bits) |
| 0x00000036 | 16 | DDR_DMAAHMW_REQCOUNTH | Memory Request Count (DMA AHM write) (hi bits) |
| 0x00000037 | 16 | DDR_DMAAHMW_REQCOUNTL | Memory Request Count (DMA AHM write) (lo bits) |
| 0x00000038 | 16 | DDR_ACC_REQCOUNTH | Memory Request Count (ACC) (hi bits) |
| 0x00000039 | 16 | DDR_ACC_REQCOUNTL | Memory Request Count (ACC) (lo bits) |
| 0x00000100 | 16 | DDR_COMPAT | Unknown |
| 0x00000101 | 16 | DDR_PROT_REG | Unknown |
| 0x00000102 | 16 | DDR_PROT_SPL | SPL protection enable/disable |
| 0x00000103 | 16 | DDR_PROT_SPL_BASE | SPL protection base address |
| 0x00000104 | 16 | DDR_PROT_SPL_END | SPL protection end address |
| 0x00000105 | 16 | DDR_PROT_DDR | DDR protection enable/disable |
| 0x00000106 | 16 | DDR_PROT_DDR_BASE | DDR protection base address |
| 0x00000107 | 16 | DDR_PROT_DDR_END | DDR protection end address |
| 0x00000108 | 16 | DDR_COLSEL | Unknown |
| 0x00000109 | 16 | DDR_ROWSEL | Unknown |
| 0x0000010a | 16 | DDR_BANKSEL | Unknown |
| 0x0000010b | 16 | DDR_RANKSEL | Unknown |
| 0x0000010c | 16 | DDR_COLMSK | Unknown |
| 0x0000010d | 16 | DDR_ROWMSK | Unknown |
| 0x0000010e | 16 | DDR_BANKMSK | Unknown |
| 0x0000010f | 16 | DDR_PROT_SPL_ERR | SPL protection error |
| 0x00000110 | 16 | DDR_PROT_DDR_ERR | DDR protection error |
| 0x00000111 | 16 | DDR_PROT_SPL_MSK | SPL protection mask |
| 0x00000112 | 16 | DDR_PROT_DDR_MSK | DDR protection mask |
| 0x00000113 | 16 | DDR_RFSH | Unknown |
| 0x00000114 | 16 | DDR_AHMFLUSH | AHM flush request |
| 0x00000115 | 16 | DDR_AHMFLUSH_ACK | AHM flush request acknowledgment |
| 0x00000134 | 16 | DDR_SEQRD_HWM | Unknown |
| 0x00000135 | 16 | DDR_SEQWR_HWM | Unknown |
| 0x00000136 | 16 | DDR_SEQCMD_HWM | Unknown |
| 0x00000137 | 16 | DDR_CPUAHM_WR_T | Unknown |
| 0x00000138 | 16 | DDR_DMAAHM_WR_T | Unknown |
| 0x00000139 | 16 | DDR_DMAAHM0_WR_T | Unknown |
| 0x0000013a | 16 | DDR_DMAAHM1_WR_T | Unknown |
| 0x0000013b | 16 | DDR_PI_WR_T | Unknown |
| 0x0000013c | 16 | DDR_PE_WR_T | Unknown |
| 0x0000013d | 16 | DDR_IO_WR_T | Unknown |
| 0x0000013e | 16 | DDR_DSP_WR_T | Unknown |
| 0x0000013f | 16 | DDR_ACC_WR_T | Unknown |
| 0x00000140 | 16 | DDR_ARB_MAXWR | Unknown |
| 0x00000141 | 16 | DDR_ARB_MINRD | Unknown |
| 0x00000142 | 16 | DDR_PROF_CPUAHM | Unknown |
| 0x00000143 | 16 | DDR_PROF_CPUAHM0 | Unknown |
| 0x00000144 | 16 | DDR_PROF_DMAAHM | Unknown |
| 0x00000145 | 16 | DDR_PROF_DMAAHM0 | Unknown |
| 0x00000146 | 16 | DDR_PROF_DMAAHM1 | Unknown |
| 0x00000147 | 16 | DDR_PROF_PI | Unknown |
| 0x00000148 | 16 | DDR_PROF_VI | Unknown |
| 0x00000149 | 16 | DDR_PROF_IO | Unknown |
| 0x0000014a | 16 | DDR_PROF_DSP | Unknown |
| 0x0000014b | 16 | DDR_PROF_TC | Unknown |
| 0x0000014c | 16 | DDR_PROF_CP | Unknown |
| 0x0000014d | 16 | DDR_PROF_ACC | Unknown |
| 0x0000014e | 16 | DDR_RDPR_CPUAHM | Unknown |
| 0x0000014f | 16 | DDR_RDPR_CPUAHM0 | Unknown |
| 0x00000150 | 16 | DDR_RDPR_DMAAHM | Unknown |
| 0x00000151 | 16 | DDR_RDPR_DMAAHM0 | Unknown |
| 0x00000152 | 16 | DDR_RDPR_DMAAHM1 | Unknown |
| 0x00000153 | 16 | DDR_RDPR_PI | Unknown |
| 0x00000154 | 16 | DDR_RDPR_VI | Unknown |
| 0x00000155 | 16 | DDR_RDPR_IO | Unknown |
| 0x00000156 | 16 | DDR_RDPR_DSP | Unknown |
| 0x00000157 | 16 | DDR_RDPR_TC | Unknown |
| 0x00000158 | 16 | DDR_RDPR_CP | Unknown |
| 0x00000159 | 16 | DDR_RDPR_ACC | Unknown |
| 0x0000015a | 16 | DDR_ARB_MAXRD | Unknown |
| 0x0000015b | 16 | DDR_ARB_MISC | Unknown |
| 0x0000015c | 16 | DDR_ARAM_EMUL | Unknown |
| 0x0000015d | 16 | DDR_WRMUX | Unknown |
| 0x0000015e | 16 | DDR_PERF | Unknown |
| 0x0000015f | 16 | DDR_PERF_READ | Unknown |
| 0x00000160 | 16 | DDR_ARB_EXADDR | Unknown |
| 0x00000161 | 16 | DDR_ARB_EXCMD | Unknown |
| 0x00000162 | 16 | DDR_SEQ_DATA | DDR SEQ register's value to read/write |
| 0x00000163 | 16 | DDR_SEQ_ADDR | DDR SEQ register's address to read/write |
| 0x00000164 | 16 | DDR_BIST_DATA | DDR BIST register's address to read/write |
| 0x00000165 | 16 | DDR_BIST_ADDR | DDR BIST register's address to read/write |
| 0x00000166 | 16 | DDR_EDRAM_REFRESH_CTRL | EDRAM refresh settings |
| 0x00000167 | 16 | DDR_EDRAM_REFRESH_VAL | EDRAM refresh value |
| 0x0000016a | 16 | DDR_MEM1_COMPAT_MODE | Unknown |
| 0x0000016b | 16 | DDR_CAFE_DDR_RANGE_TOP | Unknown |
| 0x00000180 | 16 | DDR_SEQ0_DATA | DDR SEQ0 sequential register's value to read/write |
| 0x00000181 | 16 | DDR_SEQ0_ADDR | DDR SEQ0 sequential register's address to read/write |
| 0x00000200 | 16 | DDR_BLOCK_MEM0_CFG | MEM block protection configuration for MEM0 |
| 0x00000201 | 16 | DDR_BLOCK_MEM1_CFG | MEM block protection configuration for MEM1 |
| 0x00000202 | 16 | DDR_BLOCK_MEM2_CFG | MEM block protection configuration for MEM2 |
| 0x00000203 | 16 | DDR_BLOCK_ERROR_ADDR_LOW | MEM block protection violation's address (low) |
| 0x00000204 | 16 | DDR_BLOCK_ERROR_ADDR_HIGH | MEM block protection violation's address (high) |
| 0x00000239 | 16 | DDR_BLOCK_ERROR_CID | MEM block protection violation's client ID |
| 0x0000023a | 16 | DDR_BLOCK_ERROR | MEM block protection violation's state |
| 0x00000325 | 16 | DDR_GPU_ENDIANNESS | GPU endianness control |
Register Details
SEQ
DDR sequencer registers. These are indirectly accessed through MEM_SEQ_ADDR/DDR_SEQ_ADDR and MEM_SEQ_DATA/DDR_SEQ_DATA.
Register List
| DDR controller | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x00000000 | 16 | SEQ_BL4 | Unknown |
| 0x00000001 | 16 | SEQ_TRCDR | Unknown |
| 0x00000002 | 16 | SEQ_TRCDW | Unknown |
| 0x00000003 | 16 | SEQ_TRAS | Unknown |
| 0x00000004 | 16 | SEQ_TRC | Unknown |
| 0x00000005 | 16 | SEQ_TCL | Unknown |
| 0x00000006 | 16 | SEQ_TWL | Unknown |
| 0x00000007 | 16 | SEQ_RRL | Unknown |
| 0x00000008 | 16 | SEQ_TRRD | Unknown |
| 0x00000009 | 16 | SEQ_TFAW | Unknown |
| 0x0000000a | 16 | SEQ_TRFC | Unknown |
| 0x0000000b | 16 | SEQ_TRDWR | Unknown |
| 0x0000000c | 16 | SEQ_TWRRD | Unknown |
| 0x0000000d | 16 | SEQ_TR2R | Unknown |
| 0x0000000e | 16 | SEQ_RDPR | Unknown |
| 0x0000000f | 16 | SEQ_WRPR | Unknown |
| 0x00000010 | 16 | SEQ_BANK4 | Unknown |
| 0x00000011 | 16 | SEQ_QSOE0 | Unknown |
| 0x00000012 | 16 | SEQ_QSOE1 | Unknown |
| 0x00000013 | 16 | SEQ_QSOE2 | Unknown |
| 0x00000014 | 16 | SEQ_QSOE3 | Unknown |
| 0x00000015 | 16 | SEQ_RANK2 | Unknown |
| 0x00000016 | 16 | SEQ_DDR2 | Unknown |
| 0x00000017 | 16 | SEQ_RSTB | Unknown |
| 0x00000018 | 16 | SEQ_CKEEN | Unknown |
| 0x00000019 | 16 | SEQ_CKEDYN | Unknown |
| 0x0000001a | 16 | SEQ_CKESR | Unknown |
| 0x0000001b | 16 | SEQ_ODTON | Unknown |
| 0x0000001c | 16 | SEQ_ODTDYN | Unknown |
| 0x0000001d | 16 | SEQ_ODT0 | Unknown |
| 0x0000001e | 16 | SEQ_ODT1 | Unknown |
| 0x0000001f | 16 | SEQ_RECEN0 | Unknown |
| 0x00000020 | 16 | SEQ_RECEN1 | Unknown |
| 0x00000021 | 16 | SEQ_IDLEST | Unknown |
| 0x00000022 | 16 | SEQ_NPLRD | Unknown |
| 0x00000023 | 16 | SEQ_NPLCONF | Unknown |
| 0x00000024 | 16 | SEQ_NOOPEN | Unknown |
| 0x00000025 | 16 | SEQ_QSDEF | Unknown |
| 0x00000026 | 16 | SEQ_ODTPIN | Unknown |
| 0x00000027 | 16 | SEQ_NPLDLY | Unknown |
| 0x00000028 | 16 | SEQ_STATUS | Unknown |
| 0x00000029 | 16 | SEQ_VENDORID0 | Unknown |
| 0x0000002a | 16 | SEQ_VENDORID1 | Unknown |
| 0x0000002b | 16 | SEQ_NMOSPD | Unknown |
| 0x0000002c | 16 | SEQ_STR0 | Unknown |
| 0x0000002d | 16 | SEQ_STR1 | Unknown |
| 0x0000002e | 16 | SEQ_STR2 | Unknown |
| 0x0000002f | 16 | SEQ_STR3 | Unknown |
| 0x00000030 | 16 | SEQ_APAD0 | Unknown |
| 0x00000031 | 16 | SEQ_APAD1 | Unknown |
| 0x00000032 | 16 | SEQ_CKPAD0 | Unknown |
| 0x00000033 | 16 | SEQ_CKPAD1 | Unknown |
| 0x00000034 | 16 | SEQ_CMDPAD0 | Unknown |
| 0x00000035 | 16 | SEQ_CMDPAD1 | Unknown |
| 0x00000036 | 16 | SEQ_DQPAD0 | Unknown |
| 0x00000037 | 16 | SEQ_DQPAD1 | Unknown |
| 0x00000038 | 16 | SEQ_QSPAD0 | Unknown |
| 0x00000039 | 16 | SEQ_QSPAD1 | Unknown |
| 0x0000003a | 16 | SEQ_WRDQ0 | Unknown |
| 0x0000003b | 16 | SEQ_WRDQ1 | Unknown |
| 0x0000003c | 16 | SEQ_WRQS0 | Unknown |
| 0x0000003d | 16 | SEQ_WRQS1 | Unknown |
| 0x0000003e | 16 | SEQ_MADJL | Unknown |
| 0x0000003f | 16 | SEQ_MADJH | Unknown |
| 0x00000040 | 16 | SEQ_SADJ0L | Unknown |
| 0x00000041 | 16 | SEQ_SADJ0H | Unknown |
| 0x00000042 | 16 | SEQ_SADJ1L | Unknown |
| 0x00000043 | 16 | SEQ_SADJ1H | Unknown |
| 0x00000044 | 16 | SEQ_RDDQ1 | Unknown |
| 0x00000045 | 16 | SEQ_WR | Unknown |
| 0x00000046 | 16 | SEQ_PADA | Unknown |
| 0x00000047 | 16 | SEQ_PAD0 | Unknown |
| 0x00000048 | 16 | SEQ_PAD1 | Unknown |
| 0x00000049 | 16 | SEQ_ARAM | Unknown |
| 0x0000004a | 16 | SEQ_WR2PR | Unknown |
| 0x0000004b | 16 | SEQ_SYNC | Unknown |
| 0x0000004c | 16 | SEQ_RECVON | Unknown |
Register Details
BIST
DDR built-in self-test registers. These are indirectly accessed through MEM_BIST_ADDR/DDR_BIST_ADDR and MEM_BIST_DATA/DDR_BIST_DATA.
Register List
| DDR controller | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x00000000 | 16 | BIST_EN | Unknown |
| 0x00000001 | 16 | BIST_WRGO | Unknown |
| 0x00000002 | 16 | BIST_WRRPT | Unknown |
| 0x00000003 | 16 | BIST_WRCNTH | Unknown |
| 0x00000004 | 16 | BIST_WRCNTL | Unknown |
| 0x00000005 | 16 | BIST_RDGO | Unknown |
| 0x00000006 | 16 | BIST_RDRPT | Unknown |
| 0x00000007 | 16 | BIST_RDCNTH | Unknown |
| 0x00000008 | 16 | BIST_RDCNTL | Unknown |
| 0x00000009 | 16 | BIST_WA_CH | Unknown |
| 0x0000000a | 16 | BIST_WA_CL | Unknown |
| 0x0000000b | 16 | BIST_WA_SCNTH | Unknown |
| 0x0000000c | 16 | BIST_WA_SCNTL | Unknown |
| 0x0000000d | 16 | BIST_WA_SCONH | Unknown |
| 0x0000000e | 16 | BIST_WA_SCONL | Unknown |
| 0x0000000f | 16 | BIST_RA_CH | Unknown |
| 0x00000010 | 16 | BIST_RA_CL | Unknown |
| 0x00000011 | 16 | BIST_RA_SCNTH | Unknown |
| 0x00000012 | 16 | BIST_RA_SCNTL | Unknown |
| 0x00000013 | 16 | BIST_RA_SCONH | Unknown |
| 0x00000014 | 16 | BIST_RA_SCONL | Unknown |
| 0x00000015 | 16 | BIST_WD_C0H | Unknown |
| 0x00000016 | 16 | BIST_WD_C0L | Unknown |
| 0x00000017 | 16 | BIST_WD_C1H | Unknown |
| 0x00000018 | 16 | BIST_WD_C1L | Unknown |
| 0x00000019 | 16 | BIST_WD_C2H | Unknown |
| 0x0000001a | 16 | BIST_WD_C2L | Unknown |
| 0x0000001b | 16 | BIST_WD_C3H | Unknown |
| 0x0000001c | 16 | BIST_WD_C3L | Unknown |
| 0x0000001d | 16 | BIST_WD_C4H | Unknown |
| 0x0000001e | 16 | BIST_WD_C4L | Unknown |
| 0x0000001f | 16 | BIST_WD_C5H | Unknown |
| 0x00000020 | 16 | BIST_WD_C5L | Unknown |
| 0x00000021 | 16 | BIST_WD_C6H | Unknown |
| 0x00000022 | 16 | BIST_WD_C6L | Unknown |
| 0x00000023 | 16 | BIST_WD_C7H | Unknown |
| 0x00000024 | 16 | BIST_WD_C7L | Unknown |
| 0x00000025 | 16 | BIST_WD_SCNTH | Unknown |
| 0x00000026 | 16 | BIST_WD_SCNTL | Unknown |
| 0x00000027 | 16 | BIST_WD_SCONH | Unknown |
| 0x00000028 | 16 | BIST_WD_SCONL | Unknown |
| 0x00000029 | 16 | BIST_RD_C0H | Unknown |
| 0x0000002a | 16 | BIST_RD_C0L | Unknown |
| 0x0000002b | 16 | BIST_RD_C1H | Unknown |
| 0x0000002c | 16 | BIST_RD_C1L | Unknown |
| 0x0000002d | 16 | BIST_RD_C2H | Unknown |
| 0x0000002e | 16 | BIST_RD_C2L | Unknown |
| 0x0000002f | 16 | BIST_RD_C3H | Unknown |
| 0x00000030 | 16 | BIST_RD_C3L | Unknown |
| 0x00000031 | 16 | BIST_RD_C4H | Unknown |
| 0x00000032 | 16 | BIST_RD_C4L | Unknown |
| 0x00000033 | 16 | BIST_RD_C5H | Unknown |
| 0x00000034 | 16 | BIST_RD_C5L | Unknown |
| 0x00000035 | 16 | BIST_RD_C6H | Unknown |
| 0x00000036 | 16 | BIST_RD_C6L | Unknown |
| 0x00000037 | 16 | BIST_RD_C7H | Unknown |
| 0x00000038 | 16 | BIST_RD_C7L | Unknown |
| 0x00000039 | 16 | BIST_RD_SCNTH | Unknown |
| 0x0000003a | 16 | BIST_RD_SCNTL | Unknown |
| 0x0000003b | 16 | BIST_RD_SCONH | Unknown |
| 0x0000003c | 16 | BIST_RD_SCONL | Unknown |
| 0x0000003d | 16 | BIST_RD_MSKH | Unknown |
| 0x0000003e | 16 | BIST_RD_MSKL | Unknown |
| 0x0000003f | 16 | BIST_WRIDLE | Unknown |
| 0x00000040 | 16 | BIST_RDIDLE | Unknown |
| 0x00000041 | 16 | BIST_ERRCNT | Unknown |
Register Details
DPERF
DDR performance registers. These are indirectly accessed through MEM_PERF/DDR_PERF and MEM_PERF_READ/DDR_PERF_READ.
Register List
| DDR controller | |||
|---|---|---|---|
| Address | Bits | Name | Description |
| 0x00000000 | 16 | DPERF_TIME_H | Unknown |
| 0x00000001 | 16 | DPERF_TIME_L | Unknown |
| 0x00000002 | 16 | DPERF_SEQCMD_H | Unknown |
| 0x00000003 | 16 | DPERF_SEQCMD_L | Unknown |
| 0x00000004 | 16 | DPERF_SEQDATA_H | Unknown |
| 0x00000005 | 16 | DPERF_SEQDATA_L | Unknown |
| 0x00000006 | 16 | DPERF_RF_CNT_PI_H | Unknown |
| 0x00000007 | 16 | DPERF_RF_CNT_PI_L | Unknown |
| 0x00000008 | 16 | DPERF_NREQ_DDR_PI_H | Unknown |
| 0x00000009 | 16 | DPERF_NREQ_DDR_PI_L | Unknown |
| 0x0000000a | 16 | DPERF_TREQ_DDR_PI_H | Unknown |
| 0x0000000b | 16 | DPERF_TREQ_DDR_PI_L | Unknown |
| 0x0000000c | 16 | DPERF_TACK_DDR_PI_H | Unknown |
| 0x0000000d | 16 | DPERF_TACK_DDR_PI_L | Unknown |
| 0x0000000e | 16 | DPERF_NREQ_SPL_PI_H | Unknown |
| 0x0000000f | 16 | DPERF_NREQ_SPL_PI_L | Unknown |
| 0x00000010 | 16 | DPERF_TREQ_SPL_PI_H | Unknown |
| 0x00000011 | 16 | DPERF_TREQ_SPL_PI_L | Unknown |
| 0x00000012 | 16 | DPERF_TACK_SPL_PI_H | Unknown |
| 0x00000013 | 16 | DPERF_TACK_SPL_PI_L | Unknown |
| 0x00000014 | 16 | DPERF_RF_CNT_CPUAHM_H | Unknown |
| 0x00000015 | 16 | DPERF_RF_CNT_CPUAHM_L | Unknown |
| 0x00000016 | 16 | DPERF_NREQ_DDR_CPUAHM_H | Unknown |
| 0x00000017 | 16 | DPERF_NREQ_DDR_CPUAHM_L | Unknown |
| 0x00000018 | 16 | DPERF_TREQ_DDR_CPUAHM_H | Unknown |
| 0x00000019 | 16 | DPERF_TREQ_DDR_CPUAHM_L | Unknown |
| 0x0000001a | 16 | DPERF_TACK_DDR_CPUAHM_H | Unknown |
| 0x0000001b | 16 | DPERF_TACK_DDR_CPUAHM_L | Unknown |
| 0x0000001c | 16 | DPERF_NREQ_SPL_CPUAHM_H | Unknown |
| 0x0000001d | 16 | DPERF_NREQ_SPL_CPUAHM_L | Unknown |
| 0x0000001e | 16 | DPERF_TREQ_SPL_CPUAHM_H | Unknown |
| 0x0000001f | 16 | DPERF_TREQ_SPL_CPUAHM_L | Unknown |
| 0x00000020 | 16 | DPERF_TACK_SPL_CPUAHM_H | Unknown |
| 0x00000021 | 16 | DPERF_TACK_SPL_CPUAHM_L | Unknown |
| 0x00000022 | 16 | DPERF_RF_CNT_DMAAHM_H | Unknown |
| 0x00000023 | 16 | DPERF_RF_CNT_DMAAHM_L | Unknown |
| 0x00000024 | 16 | DPERF_NREQ_DDR_DMAAHM_H | Unknown |
| 0x00000025 | 16 | DPERF_NREQ_DDR_DMAAHM_L | Unknown |
| 0x00000026 | 16 | DPERF_TREQ_DDR_DMAAHM_H | Unknown |
| 0x00000027 | 16 | DPERF_TREQ_DDR_DMAAHM_L | Unknown |
| 0x00000028 | 16 | DPERF_TACK_DDR_DMAAHM_H | Unknown |
| 0x00000029 | 16 | DPERF_TACK_DDR_DMAAHM_L | Unknown |
| 0x0000002a | 16 | DPERF_NREQ_SPL_DMAAHM_H | Unknown |
| 0x0000002b | 16 | DPERF_NREQ_SPL_DMAAHM_L | Unknown |
| 0x0000002c | 16 | DPERF_TREQ_SPL_DMAAHM_H | Unknown |
| 0x0000002d | 16 | DPERF_TREQ_SPL_DMAAHM_L | Unknown |
| 0x0000002e | 16 | DPERF_TACK_SPL_DMAAHM_H | Unknown |
| 0x0000002f | 16 | DPERF_TACK_SPL_DMAAHM_L | Unknown |
| 0x00000030 | 16 | DPERF_RF_CNT_VI_H | Unknown |
| 0x00000031 | 16 | DPERF_RF_CNT_VI_L | Unknown |
| 0x00000032 | 16 | DPERF_NREQ_DDR_VI_H | Unknown |
| 0x00000033 | 16 | DPERF_NREQ_DDR_VI_L | Unknown |
| 0x00000034 | 16 | DPERF_TREQ_DDR_VI_H | Unknown |
| 0x00000035 | 16 | DPERF_TREQ_DDR_VI_L | Unknown |
| 0x00000036 | 16 | DPERF_TACK_DDR_VI_H | Unknown |
| 0x00000037 | 16 | DPERF_TACK_DDR_VI_L | Unknown |
| 0x00000038 | 16 | DPERF_NREQ_SPL_VI_H | Unknown |
| 0x00000039 | 16 | DPERF_NREQ_SPL_VI_L | Unknown |
| 0x0000003a | 16 | DPERF_TREQ_SPL_VI_H | Unknown |
| 0x0000003b | 16 | DPERF_TREQ_SPL_VI_L | Unknown |
| 0x0000003c | 16 | DPERF_TACK_SPL_VI_H | Unknown |
| 0x0000003d | 16 | DPERF_TACK_SPL_VI_L | Unknown |
| 0x0000003e | 16 | DPERF_RF_CNT_IO_H | Unknown |
| 0x0000003f | 16 | DPERF_RF_CNT_IO_L | Unknown |
| 0x00000040 | 16 | DPERF_NREQ_DDR_IO_H | Unknown |
| 0x00000041 | 16 | DPERF_NREQ_DDR_IO_L | Unknown |
| 0x00000042 | 16 | DPERF_TREQ_DDR_IO_H | Unknown |
| 0x00000043 | 16 | DPERF_TREQ_DDR_IO_L | Unknown |
| 0x00000044 | 16 | DPERF_TACK_DDR_IO_H | Unknown |
| 0x00000045 | 16 | DPERF_TACK_DDR_IO_L | Unknown |
| 0x00000046 | 16 | DPERF_NREQ_SPL_IO_H | Unknown |
| 0x00000047 | 16 | DPERF_NREQ_SPL_IO_L | Unknown |
| 0x00000048 | 16 | DPERF_TREQ_SPL_IO_H | Unknown |
| 0x00000049 | 16 | DPERF_TREQ_SPL_IO_L | Unknown |
| 0x0000004a | 16 | DPERF_TACK_SPL_IO_H | Unknown |
| 0x0000004b | 16 | DPERF_TACK_SPL_IO_L | Unknown |
| 0x0000004c | 16 | DPERF_RF_CNT_DSP_H | Unknown |
| 0x0000004d | 16 | DPERF_RF_CNT_DSP_L | Unknown |
| 0x0000004e | 16 | DPERF_NREQ_DDR_DSP_H | Unknown |
| 0x0000004f | 16 | DPERF_NREQ_DDR_DSP_L | Unknown |
| 0x00000050 | 16 | DPERF_TREQ_DDR_DSP_H | Unknown |
| 0x00000051 | 16 | DPERF_TREQ_DDR_DSP_L | Unknown |
| 0x00000052 | 16 | DPERF_TACK_DDR_DSP_H | Unknown |
| 0x00000053 | 16 | DPERF_TACK_DDR_DSP_L | Unknown |
| 0x00000054 | 16 | DPERF_NREQ_SPL_DSP_H | Unknown |
| 0x00000055 | 16 | DPERF_NREQ_SPL_DSP_L | Unknown |
| 0x00000056 | 16 | DPERF_TREQ_SPL_DSP_H | Unknown |
| 0x00000057 | 16 | DPERF_TREQ_SPL_DSP_L | Unknown |
| 0x00000058 | 16 | DPERF_TACK_SPL_DSP_H | Unknown |
| 0x00000059 | 16 | DPERF_TACK_SPL_DSP_L | Unknown |
| 0x0000005a | 16 | DPERF_RF_CNT_TC_H | Unknown |
| 0x0000005b | 16 | DPERF_RF_CNT_TC_L | Unknown |
| 0x0000005c | 16 | DPERF_NREQ_DDR_TC_H | Unknown |
| 0x0000005d | 16 | DPERF_NREQ_DDR_TC_L | Unknown |
| 0x0000005e | 16 | DPERF_TREQ_DDR_TC_H | Unknown |
| 0x0000005f | 16 | DPERF_TREQ_DDR_TC_L | Unknown |
| 0x00000060 | 16 | DPERF_TACK_DDR_TC_H | Unknown |
| 0x00000061 | 16 | DPERF_TACK_DDR_TC_L | Unknown |
| 0x00000062 | 16 | DPERF_NREQ_SPL_TC_H | Unknown |
| 0x00000063 | 16 | DPERF_NREQ_SPL_TC_L | Unknown |
| 0x00000064 | 16 | DPERF_TREQ_SPL_TC_H | Unknown |
| 0x00000065 | 16 | DPERF_TREQ_SPL_TC_L | Unknown |
| 0x00000066 | 16 | DPERF_TACK_SPL_TC_H | Unknown |
| 0x00000067 | 16 | DPERF_TACK_SPL_TC_L | Unknown |
| 0x00000068 | 16 | DPERF_RF_CNT_CP_H | Unknown |
| 0x00000069 | 16 | DPERF_RF_CNT_CP_L | Unknown |
| 0x0000006a | 16 | DPERF_NREQ_DDR_CP_H | Unknown |
| 0x0000006b | 16 | DPERF_NREQ_DDR_CP_L | Unknown |
| 0x0000006c | 16 | DPERF_TREQ_DDR_CP_H | Unknown |
| 0x0000006d | 16 | DPERF_TREQ_DDR_CP_L | Unknown |
| 0x0000006e | 16 | DPERF_TACK_DDR_CP_H | Unknown |
| 0x0000006f | 16 | DPERF_TACK_DDR_CP_L | Unknown |
| 0x00000070 | 16 | DPERF_NREQ_SPL_CP_H | Unknown |
| 0x00000071 | 16 | DPERF_NREQ_SPL_CP_L | Unknown |
| 0x00000072 | 16 | DPERF_TREQ_SPL_CP_H | Unknown |
| 0x00000073 | 16 | DPERF_TREQ_SPL_CP_L | Unknown |
| 0x00000074 | 16 | DPERF_TACK_SPL_CP_H | Unknown |
| 0x00000075 | 16 | DPERF_TACK_SPL_CP_L | Unknown |
| 0x00000076 | 16 | DPERF_RF_CNT_ACC_H | Unknown |
| 0x00000077 | 16 | DPERF_RF_CNT_ACC_L | Unknown |
| 0x00000078 | 16 | DPERF_NREQ_DDR_ACC_H | Unknown |
| 0x00000079 | 16 | DPERF_NREQ_DDR_ACC_L | Unknown |
| 0x0000007a | 16 | DPERF_TREQ_DDR_ACC_H | Unknown |
| 0x0000007b | 16 | DPERF_TREQ_DDR_ACC_L | Unknown |
| 0x0000007c | 16 | DPERF_TACK_DDR_ACC_H | Unknown |
| 0x0000007d | 16 | DPERF_TACK_DDR_ACC_L | Unknown |
| 0x0000007e | 16 | DPERF_NREQ_SPL_ACC_H | Unknown |
| 0x0000007f | 16 | DPERF_NREQ_SPL_ACC_L | Unknown |
| 0x00000080 | 16 | DPERF_TREQ_SPL_ACC_H | Unknown |
| 0x00000081 | 16 | DPERF_TREQ_SPL_ACC_L | Unknown |
| 0x00000082 | 16 | DPERF_TACK_SPL_ACC_H | Unknown |
| 0x00000083 | 16 | DPERF_TACK_SPL_ACC_L | Unknown |