AHM
AHM (short for AHB_MEM) is a custom bridge responsible for connecting the AHB bus to the Memory Controller.
Register List
| AHM controller
|
| Address
|
Bits
|
Name
|
Description
|
| 0x0d8b0000
|
32
|
AHM_SECDDR
|
AHM DDR memory security
|
| 0x0d8b0004
|
32
|
AHM_SECSPL
|
AHM SPLASH memory security
|
| 0x0d8b0008
|
32
|
AHM_RDBI
|
AHM read data buffer invalidate mask
|
| 0x0d8b0010
|
32
|
AHM_PREFCFG
|
AHM prefetch configuration
|
| 0x0d8b0020
|
32
|
AHM_INTMSK
|
AHM interrupt mask
|
| 0x0d8b0030
|
32
|
AHM_INTSTS
|
AHM interrupt status
|
| 0x0d8b0040
|
32
|
UNKNOWN
|
Unknown
|
| 0x0d8b0044
|
32
|
UNKNOWN
|
Unknown
|
| 0x0d8b0100...0x0d8b0300
|
32
|
AHM_PROTDDR
|
Each register controls access protection for one page of DDR memory (page size depends on AHM_SECDDR)
|
| 0x0d8b0500...0x0d8b0700
|
32
|
AHM_PROTSPL
|
Each register controls access protection for one page of SPLASH memory (page size depends on AHM_SECSPL)
|
Register Details
AHMN
The Latte hardware contains an enhanced version of AHB_MEM dubbed AHMN which, not only extends the previous AHM design, but also implements a custom XN (eXecute Never) solution to compensate for the lack of XN bit support on the Starbuck (ARM926EJ-S).
Register List
| AHMN controller
|
| Address
|
Bits
|
Name
|
Description
|
| 0x0d8b0800
|
32
|
AHMN_SECMEM0
|
AHMN MEM0 memory security
|
| 0x0d8b0804
|
32
|
AHMN_SECMEM1
|
AHMN MEM1 memory security
|
| 0x0d8b0808
|
32
|
AHMN_SECMEM2
|
AHMN MEM2 memory security
|
| 0x0d8b080c
|
32
|
AHMN_RDBI
|
AHMN read data buffer invalidate mask
|
| 0x0d8b0820
|
32
|
AHMN_INTMSK
|
AHMN interrupt mask
|
| 0x0d8b0824
|
32
|
AHMN_INTSTS
|
AHMN interrupt status
|
| 0x0d8b0840
|
32
|
UNKNOWN
|
Unknown
|
| 0x0d8b0844
|
32
|
UNKNOWN
|
Unknown
|
| 0x0d8b0850
|
32
|
AHMN_TRFSTS
|
AHMN transfer status
|
| 0x0d8b0854
|
32
|
AHMN_WORKAROUND
|
Unknown
|
| 0x0d8b0900...0x0d8b0980
|
32
|
AHMN_PROTMEM0
|
Each register controls access protection for one page of MEM0 memory (page size depends on AHMN_SECMEM0)
|
| 0x0d8b0a00...0x0d8b0c00
|
32
|
AHMN_PROTMEM1
|
Each register controls access protection for one page of MEM1 memory (page size depends on AHMN_SECMEM1)
|
| 0x0d8b0c00...0x0d8b1000
|
32
|
AHMN_PROTMEM2
|
Each register controls access protection for one page of MEM2 memory (page size depends on AHMN_SECMEM2)
|
Register Details