WiiUBrew

Difference between revisions of "Hardware/Latte IRQs"

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m (Hexkyz moved page Hardware/Latte IRQ controller to Hardware/Latte IRQs: Match wiibrew)
 
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Line 47: Line 47:
 
| 7 || ALL || SD0 ({{hw|SD Host Controller}})
 
| 7 || ALL || SD0 ({{hw|SD Host Controller}})
 
|-
 
|-
−
| 7 || LATTE || Unknown
+
| 7 || LATTE || BMD2
 
|-
 
|-
 
| 8 || ALL || SD1 ({{hw|802.11 Wireless}})
 
| 8 || ALL || SD1 ({{hw|802.11 Wireless}})
Line 53: Line 53:
 
| 8 || LATTE || AES1 ({{hw|AES Engine}} for AESS)
 
| 8 || LATTE || AES1 ({{hw|AES Engine}} for AESS)
 
|-
 
|-
−
| 9 || ALL || Reserved
+
| 9 || ALL || BFM
 
|-
 
|-
 
| 9 || LATTE || SHA1 ({{hw|SHA-1 Engine}} for SHAS-1)
 
| 9 || LATTE || SHA1 ({{hw|SHA-1 Engine}} for SHAS-1)
Line 59: Line 59:
 
| 10 || ALL || GPIPPC ({{hw|Latte GPIOs}} for Espresso)
 
| 10 || ALL || GPIPPC ({{hw|Latte GPIOs}} for Espresso)
 
|-
 
|-
−
| 10 || LATTE || Unknown
+
| 10 || LATTE || AI2
 
|-
 
|-
 
| 11 || ALL || GPIIOP ({{hw|Latte GPIOs}} for Starbuck)
 
| 11 || ALL || GPIIOP ({{hw|Latte GPIOs}} for Starbuck)
Line 65: Line 65:
 
| 11 || LATTE || GPU7_GC
 
| 11 || LATTE || GPU7_GC
 
|-
 
|-
−
| 12 || ALL || DBGINT
+
| 12 || ALL || AHBDBG
 
|-
 
|-
 
| 12 || LATTE || IOP2X
 
| 12 || LATTE || IOP2X
Line 79: Line 79:
 
| 15 || ALL || SYSRSTB
 
| 15 || ALL || SYSRSTB
 
|-
 
|-
−
| 15 || LATTE || Reserved
+
| 15 || LATTE || PAD0
 
|-
 
|-
 
| 16 || ALL || VIVSYNC
 
| 16 || ALL || VIVSYNC
Line 85: Line 85:
 
| 16 || LATTE || Reserved
 
| 16 || LATTE || Reserved
 
|-
 
|-
−
| 17 || ALL || Power button
+
| 17 || ALL || RSW
 
|-
 
|-
 
| 17 || LATTE || Reserved
 
| 17 || LATTE || Reserved
Line 93: Line 93:
 
| 18 || LATTE || Reserved
 
| 18 || LATTE || Reserved
 
|-
 
|-
−
| 19 || ALL || Reserved
+
| 19 || ALL || SI
 
|-
 
|-
 
| 19 || LATTE || Reserved
 
| 19 || LATTE || Reserved
Line 101: Line 101:
 
| 20 || LATTE || Reserved
 
| 20 || LATTE || Reserved
 
|-
 
|-
−
| 21 || ALL || Reserved
+
| 21 || ALL || AI
 
|-
 
|-
 
| 21 || LATTE || Reserved
 
| 21 || LATTE || Reserved
 
|-
 
|-
−
| 22 || ALL || Reserved
+
| 22 || ALL || DSP
 
|-
 
|-
 
| 22 || LATTE || Reserved
 
| 22 || LATTE || Reserved
 
|-
 
|-
−
| 23 || ALL || Reserved
+
| 23 || ALL || MEM
 
|-
 
|-
 
| 23 || LATTE || Reserved
 
| 23 || LATTE || Reserved
 
|-
 
|-
−
| 24 || ALL || Reserved
+
| 24 || ALL || VI
 
|-
 
|-
 
| 24 || LATTE || Reserved
 
| 24 || LATTE || Reserved
 
|-
 
|-
−
| 25 || ALL || Reserved
+
| 25 || ALL || PEINT0
 
|-
 
|-
 
| 25 || LATTE || Reserved
 
| 25 || LATTE || Reserved
 
|-
 
|-
−
| 26 || ALL || Reserved
+
| 26 || ALL || PEINT1
 
|-
 
|-
 
| 26 || LATTE || IPC_PPC2 (Espresso CPU2)
 
| 26 || LATTE || IPC_PPC2 (Espresso CPU2)
 
|-
 
|-
−
| 27 || ALL || Reserved
+
| 27 || ALL || CP
 
|-
 
|-
 
| 27 || LATTE || IPC_IOP2 (Starbuck CPU2)
 
| 27 || LATTE || IPC_IOP2 (Starbuck CPU2)
 
|-
 
|-
−
| 28 || ALL || {{hw|SATA Controller}} (DBGINT only?)
+
| 28 || ALL || DBG
 
|-
 
|-
 
| 28 || LATTE || IPC_PPC1 (Espresso CPU1)
 
| 28 || LATTE || IPC_PPC1 (Espresso CPU1)
 
|-
 
|-
−
| 29 || ALL || Reserved
+
| 29 || ALL || SD
 
|-
 
|-
 
| 29 || LATTE || IPC_IOP1 (Starbuck CPU1)
 
| 29 || LATTE || IPC_IOP1 (Starbuck CPU1)
 
|-
 
|-
−
| 30 || ALL || IPC for Espresso in compat mode
+
| 30 || ALL || IPCPPC (Espresso in compat mode)
 
|-
 
|-
 
| 30 || LATTE || IPC_PPC0 (Espresso CPU0)
 
| 30 || LATTE || IPC_PPC0 (Espresso CPU0)
 
|-
 
|-
−
| 31 || ALL || IPC for Starbuck in compat mode
+
| 31 || ALL || IPCIOP (Starbuck in compat mode)
 
|-
 
|-
 
| 31 || LATTE || IPC_IOP0 (Starbuck CPU0)
 
| 31 || LATTE || IPC_IOP0 (Starbuck CPU0)
Line 161: Line 161:
 
=== Latte block ===
 
=== Latte block ===
 
{{reglist|Latte block - PPC core 0}}
 
{{reglist|Latte block - PPC core 0}}
−
{{rla|0x0d800440|32|LT_PPC0INTSTSALL|Triggered IRQs for PPC core 0 (Wood and Latte)}}
+
{{rla|0x0d800440|32|LT_PPC0INT1STS|Triggered IRQs for PPC core 0 (Wood and Latte)}}
−
{{rla|0x0d800444|32|LT_PPC0INTSTSLATTE|Triggered IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d800444|32|LT_PPC0INT2STS|Triggered IRQs for PPC core 0 (Latte only)}}
−
{{rla|0x0d800448|32|LT_PPC0INTENALL|Allowed IRQs for PPC core 0 (Wood and Latte)}}
+
{{rla|0x0d800448|32|LT_PPC0INT1EN|Allowed IRQs for PPC core 0 (Wood and Latte)}}
−
{{rla|0x0d80044c|32|LT_PPC0INTENLATTE|Allowed IRQs for PPC core 0 (Latte only)}}
+
{{rla|0x0d80044c|32|LT_PPC0INT2EN|Allowed IRQs for PPC core 0 (Latte only)}}
 
|}
 
|}
  
 
{{reglist|Latte block - PPC core 1}}
 
{{reglist|Latte block - PPC core 1}}
−
{{rla|0x0d800450|32|LT_PPC1INTSTSALL|Triggered IRQs for PPC core 1 (Wood and Latte)}}
+
{{rla|0x0d800450|32|LT_PPC1INT1STS|Triggered IRQs for PPC core 1 (Wood and Latte)}}
−
{{rla|0x0d800454|32|LT_PPC1INTSTSLATTE|Triggered IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d800454|32|LT_PPC1INT2STS|Triggered IRQs for PPC core 1 (Latte only)}}
−
{{rla|0x0d800458|32|LT_PPC1INTENALL|Allowed IRQs for PPC core 1 (Wood and Latte)}}
+
{{rla|0x0d800458|32|LT_PPC1INT1EN|Allowed IRQs for PPC core 1 (Wood and Latte)}}
−
{{rla|0x0d80045c|32|LT_PPC1INTENLATTE|Allowed IRQs for PPC core 1 (Latte only)}}
+
{{rla|0x0d80045c|32|LT_PPC1INT2EN|Allowed IRQs for PPC core 1 (Latte only)}}
 
|}
 
|}
  
 
{{reglist|Latte block - PPC core 2}}
 
{{reglist|Latte block - PPC core 2}}
−
{{rla|0x0d800460|32|LT_PPC2INTSTSALL|Triggered IRQs for PPC core 2 (Wood and Latte)}}
+
{{rla|0x0d800460|32|LT_PPC2INT1STS|Triggered IRQs for PPC core 2 (Wood and Latte)}}
−
{{rla|0x0d800464|32|LT_PPC2INTSTSLATTE|Triggered IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d800464|32|LT_PPC2INT2STS|Triggered IRQs for PPC core 2 (Latte only)}}
−
{{rla|0x0d800468|32|LT_PPC2INTENALL|Allowed IRQs for PPC core 2 (Wood and Latte)}}
+
{{rla|0x0d800468|32|LT_PPC2INT1EN|Allowed IRQs for PPC core 2 (Wood and Latte)}}
−
{{rla|0x0d80046c|32|LT_PPC2INTENLATTE|Allowed IRQs for PPC core 2 (Latte only)}}
+
{{rla|0x0d80046c|32|LT_PPC2INT2EN|Allowed IRQs for PPC core 2 (Latte only)}}
 
|}
 
|}
  
 
{{reglist|Latte block - ARM core}}
 
{{reglist|Latte block - ARM core}}
−
{{rla|0x0d800470|32|LT_IOPINTSTSALL|Triggered IRQs for ARM core (Wood and Latte)}}
+
{{rla|0x0d800470|32|LT_IOPINT1STS|Triggered IRQs for ARM core (Wood and Latte)}}
−
{{rla|0x0d800474|32|LT_IOPINTSTSLATTE|Triggered IRQs for ARM core (Latte only)}}
+
{{rla|0x0d800474|32|LT_IOPINT2STS|Triggered IRQs for ARM core (Latte only)}}
−
{{rla|0x0d800478|32|LT_IOPIRQINTENALL|Allowed IRQs for ARM core (Wood and Latte)}}
+
{{rla|0x0d800478|32|LT_IOPIRQINT1EN|Allowed IRQs for ARM core (Wood and Latte)}}
−
{{rla|0x0d80047c|32|LT_IOPIRQINTENLATTE|Allowed IRQs for ARM core (Latte only)}}
+
{{rla|0x0d80047c|32|LT_IOPIRQINT2EN|Allowed IRQs for ARM core (Latte only)}}
−
{{rld|0x0d800480|32|LT_IOPFIQINTENALL|Allowed FIQs for the ARM core (Wood and Latte)}}
+
{{rld|0x0d800480|32|LT_IOPFIQINT1EN|Allowed FIQs for the ARM core (Wood and Latte)}}
−
{{rld|0x0d800484|32|LT_IOPFIQINTENLATTE|Allowed FIQs for the ARM core (Latte only)}}
+
{{rld|0x0d800484|32|LT_IOPFIQINT2EN|Allowed FIQs for the ARM core (Latte only)}}
 
|}
 
|}
  
 
== Register descriptions ==
 
== Register descriptions ==
−
{{regsimple|LT_PPCxINTSTSALL|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCxINT1STS|addr=0x0d800440/0x0d800450/0x0d800460|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_PPCxINTSTSLATTE|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
+
{{regsimple|LT_PPCxINT2STS|addr=0x0d800444/0x0d800454/0x0d800464|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_PPCxINTENALL|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
+
{{regsimple|LT_PPCxINT1EN|addr=0x0d800448/0x0d800458/0x0d800468|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
−
{{regsimple|LT_PPCxINTENLATTE|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
+
{{regsimple|LT_PPCxINT2EN|addr=0x0d80044c/0x0d80045c/0x0d80046c|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause [[Hardware/Processor_Interface|Processor Interface]] IRQ #12 to be generated.
 
----
 
----
−
{{regsimple|LT_IOPINTSTSALL|addr=0x0d800470|bits=32|access=R/Z}}
+
{{regsimple|LT_IOPINT1STS|addr=0x0d800470|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_IOPINTSTSLATTE|addr=0x0d800474|bits=32|access=R/Z}}
+
{{regsimple|LT_IOPINT2STS|addr=0x0d800474|bits=32|access=R/Z}}
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write ''1'' to it.
 
----
 
----
−
{{regsimple|LT_IOPIRQINTENALL|addr=0x0d800478|bits=32|access=R/W}}
+
{{regsimple|LT_IOPIRQINT1EN|addr=0x0d800478|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
 
----
 
----
−
{{regsimple|LT_IOPIRQINTENLATTE|addr=0x0d80047c|bits=32|access=R/W}}
+
{{regsimple|LT_IOPIRQINT2EN|addr=0x0d80047c|bits=32|access=R/W}}
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.
 
This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.

Latest revision as of 00:30, 22 April 2025

The Latte chipset contains a dual interrupt controller similar to the one found in the old Hollywood's chipset. This controller is able to route up to 64 interrupt sources to the Starbuck, the Espresso, or both. IOSU distinguishes interrupt sources common to Wood and Latte hardware (ALL) and new sources that are exclusive to the Latte (LATTE).

Latte IRQs
Access
EspressoPartial
StarbuckFull
Registers
Base0x0d800030, 0x0d800440
Length0x14, 0x48
Access size32 bits
Byte orderBig Endian
This box: view • talk • edit

IRQ Sources

Bit Group Description
0 ALL TMR (Timer)
0 LATTE SD2 (SD Host Controller for eMMC)
1 ALL FLA (NAND Interface)
1 LATTE SD3 (SD Host Controller for Toucan)
2 ALL AES0 (AES Engine)
2 LATTE EHCI1 (USB Host Controller)
3 ALL SHA0 (SHA-1 Engine)
3 LATTE OHCI10 (USB Host Controller)
4 ALL EHCI0 (USB Host Controller)
4 LATTE EHCI2 (USB Host Controller)
5 ALL OHCI0 (USB Host Controller)
5 LATTE OHCI20 (USB Host Controller)
6 ALL OHCI1 (USB Host Controller)
6 LATTE SATA (SATA Controller)
7 ALL SD0 (SD Host Controller)
7 LATTE BMD2
8 ALL SD1 (802.11 Wireless)
8 LATTE AES1 (AES Engine for AESS)
9 ALL BFM
9 LATTE SHA1 (SHA-1 Engine for SHAS-1)
10 ALL GPIPPC (Latte GPIOs for Espresso)
10 LATTE AI2
11 ALL GPIIOP (Latte GPIOs for Starbuck)
11 LATTE GPU7_GC
12 ALL AHBDBG
12 LATTE IOP2X
13 ALL VIPIWR
13 LATTE PRIMARY_I2C (for Espresso)
14 ALL SIEMU
14 LATTE SECONDARY_I2C (for Starbuck)
15 ALL SYSRSTB
15 LATTE PAD0
16 ALL VIVSYNC
16 LATTE Reserved
17 ALL RSW
17 LATTE Reserved
18 ALL DI
18 LATTE Reserved
19 ALL SI
19 LATTE Reserved
20 ALL EXI
20 LATTE Reserved
21 ALL AI
21 LATTE Reserved
22 ALL DSP
22 LATTE Reserved
23 ALL MEM
23 LATTE Reserved
24 ALL VI
24 LATTE Reserved
25 ALL PEINT0
25 LATTE Reserved
26 ALL PEINT1
26 LATTE IPC_PPC2 (Espresso CPU2)
27 ALL CP
27 LATTE IPC_IOP2 (Starbuck CPU2)
28 ALL DBG
28 LATTE IPC_PPC1 (Espresso CPU1)
29 ALL SD
29 LATTE IPC_IOP1 (Starbuck CPU1)
30 ALL IPCPPC (Espresso in compat mode)
30 LATTE IPC_PPC0 (Espresso CPU0)
31 ALL IPCIOP (Starbuck in compat mode)
31 LATTE IPC_IOP0 (Starbuck CPU0)

Register List

Each CPU has an independent set of control registers and this set is subdivided into two main blocks: one for Wood and Latte hardware and another exclusive to Latte hardware. The subset used for Latte is further subdivided as a SMP block that serves the 3 PPC cores and the ARM core.

Wood block

Wood block
Address Bits Name Description
0x0d800030 32 HW_PPCINTSTS Triggered IRQs for the PPC core in vWii
0x0d800034 32 HW_PPCINTEN Allowed IRQs for the PPC core in vWii
0x0d800038 32 HW_IOPINTSTS Triggered IRQs for the ARM core in vWii
0x0d80003c 32 HW_IOPIRQINTEN Allowed IRQs for the ARM core in vWii
0x0d800040 32 HW_IOPFIQINTEN Allowed FIQs for the ARM core in vWii

Latte block

Latte block - PPC core 0
Address Bits Name Description
0x0d800440 32 LT_PPC0INT1STS Triggered IRQs for PPC core 0 (Wood and Latte)
0x0d800444 32 LT_PPC0INT2STS Triggered IRQs for PPC core 0 (Latte only)
0x0d800448 32 LT_PPC0INT1EN Allowed IRQs for PPC core 0 (Wood and Latte)
0x0d80044c 32 LT_PPC0INT2EN Allowed IRQs for PPC core 0 (Latte only)
Latte block - PPC core 1
Address Bits Name Description
0x0d800450 32 LT_PPC1INT1STS Triggered IRQs for PPC core 1 (Wood and Latte)
0x0d800454 32 LT_PPC1INT2STS Triggered IRQs for PPC core 1 (Latte only)
0x0d800458 32 LT_PPC1INT1EN Allowed IRQs for PPC core 1 (Wood and Latte)
0x0d80045c 32 LT_PPC1INT2EN Allowed IRQs for PPC core 1 (Latte only)
Latte block - PPC core 2
Address Bits Name Description
0x0d800460 32 LT_PPC2INT1STS Triggered IRQs for PPC core 2 (Wood and Latte)
0x0d800464 32 LT_PPC2INT2STS Triggered IRQs for PPC core 2 (Latte only)
0x0d800468 32 LT_PPC2INT1EN Allowed IRQs for PPC core 2 (Wood and Latte)
0x0d80046c 32 LT_PPC2INT2EN Allowed IRQs for PPC core 2 (Latte only)
Latte block - ARM core
Address Bits Name Description
0x0d800470 32 LT_IOPINT1STS Triggered IRQs for ARM core (Wood and Latte)
0x0d800474 32 LT_IOPINT2STS Triggered IRQs for ARM core (Latte only)
0x0d800478 32 LT_IOPIRQINT1EN Allowed IRQs for ARM core (Wood and Latte)
0x0d80047c 32 LT_IOPIRQINT2EN Allowed IRQs for ARM core (Latte only)
0x0d800480 32 LT_IOPFIQINT1EN Allowed FIQs for the ARM core (Wood and Latte)
0x0d800484 32 LT_IOPFIQINT2EN Allowed FIQs for the ARM core (Latte only)

Register descriptions

LT_PPCxINT1STS (0x0d800440/0x0d800450/0x0d800460)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.

LT_PPCxINT2STS (0x0d800444/0x0d800454/0x0d800464)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Espresso. These are set by the hardware. To clear a flag, write 1 to it.

LT_PPCxINT1EN (0x0d800448/0x0d800458/0x0d800468)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.

LT_PPCxINT2EN (0x0d80044c/0x0d80045c/0x0d80046c)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Espresso. If a bit is set, then the corresponding flag bit will cause Processor Interface IRQ #12 to be generated.

LT_IOPINT1STS (0x0d800470)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.

LT_IOPINT2STS (0x0d800474)
  310
Access R/Z

This register contains the 32 IRQ flag bits for the Starbuck. These are set by the hardware. To clear a flag, write 1 to it.

LT_IOPIRQINT1EN (0x0d800478)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.

LT_IOPIRQINT2EN (0x0d80047c)
  310
Access R/W

This register contains the 32 IRQ mask bits for the Starbuck. If a bit is set, then the corresponding flag bit will cause the IOP IRQ to be asserted.

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